• Title/Summary/Keyword: 유도 알고리듬

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Modeling TCP Loss Recovery for Random Packet Losses (임의 패킷 손실에 대한 TCP의 손실 복구 과정 모델링 및 분석)

  • Kim, Beom-Joon;Kim, Dong-Yeon;Lee, Jai-Yong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.4B
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    • pp.288-297
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    • 2003
  • The fast retransmit and fast recovery algorithm of TCP Reno, when multiple packets in the same window are lost, cannot recover them without RTO (Retransmission Timeout). TCP New-Reno can recover multiple lost packets by extending fast recovery using partial acknowledgement. If the retransmitted packet is lost again during fast recovery, however, RTO cannot be avoided. In this paper, we propose an algorithm called "Duplicate Acknowledgement Counting(DAC)" to alleviate this problem. DAC can detect the retransmitted packet loss by counting duplicate ACKs. Conditions that a lost packet can be recovered by loss recovery of TCP Reno, TCP New-Reno and TCP New-Reno using DAC are derived by modeling loss recovery behavior of each TCP. We calculate the loss recovery probability for random packet loss probability numerically, and show that DAC can improve loss recovery behavior of TCP New-Reno.

Object Tracking Using Adaptive Scale Factor Neural Network (적응형 스케일조절 신경망을 이용한 객체 위치 추적)

  • Sun-Bae Park;Do-Sik Yoo
    • Journal of Advanced Navigation Technology
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    • v.26 no.6
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    • pp.522-527
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    • 2022
  • Object tracking is a field of signal processing that sequentially tracks the location of an object based on the previous-time location estimations and the present-time observation data. In this paper, we propose an adaptive scaling neural network that can track and adjust the scale of the input data with three recursive neural network (RNN) submodules. To evaluate object tracking performance, we compare the proposed system with the Kalman filter and the maximum likelihood object tracking scheme under an one-dimensional object movement model in which the object moves with piecewise constant acceleration. We show that the proposed scheme is generally better, in terms of root mean square error (RMSE) performance, than maximum likelihood scheme and Kalman filter and that the performance gaps grow with increased observation noise.

Classification of Estuaries based on Morphological Convergence (형태적 수렴 특성을 이용한 하구 분류)

  • SHIN, Hyun-jung;RHEW, Hosahng;LEE, Guan-hong
    • Journal of The Geomorphological Association of Korea
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    • v.19 no.3
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    • pp.1-22
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    • 2012
  • The classification scheme of estuaries can be divided into two categories: qualitative classification based on geomorphic characteristics and quantitative classification based upon the physical properties of water body. While simple and intuitive scheme of the former is difficult to quantify, the latter is not easy to apply due to the lack of data. A classification scheme based on morphological convergence is very promising because it only requires easily accessible data such as width and depth of channels, as well as it can characterize estuaries in terms of tidal propagation. Thus, this paper examines the classification scheme based on estuarine morphological convergence using depth and width data obtained from 19 major Korean estuaries. Morphological convergence for each estuary was estimated with the estuarine length, width and depth data to get the convergence parameters, which includes the degree of funneling ${\nu}$ and the dimensionless estuarine length $y_0$. The transfer function ${\xi}({\nu},ky)$ is then deduced analytically from 1D depth-integrated hydrodynamic momentum equation and continuity equation for estuarine shapes. Tidal response of each estuary is finally calculated using ${\nu}$, $y_0$ and ${\xi}({\nu},ky)$ for comparison and classification. The 19 Korean estuaries were classified into three groups: tidal amplitude-dominated estuaries with standing wave-like tidal response (group 1), current-dominated estuaries with progressive wave-like tidal response (group 2), and the intermediate group (group 3) between groups 1 and 2. The sensitivity analysis revealed that uncertainties in determining the estuarine length can have a critical effect upon the results of classification, which indicates that the reasonable determination of the estuarine length is of critical importance. Once the estuarine length is feasibly determined, depth-convergence can be neglected without any negative effect on the classification scheme, which has an important ramification on the wide applicability of the classification scheme.

Active and Passive Suppression of Composite Panel Flutter Using Piezoceramics with Shunt Circuits (션트회로에 연결된 압전세라믹을 이용한 복합재료 패널 플리터의 능동 및 수동 제어)

  • 문성환;김승조
    • Composites Research
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    • v.13 no.5
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    • pp.50-59
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    • 2000
  • In this paper, two methods to suppress flutter of the composite panel are examined. First, in the active control method, a controller based on the linear optimal control theory is designed and control input voltage is applied on the actuators and a PZT is used as actuator. Second, a new technique, passive suppression scheme, is suggested for suppression of the nonlinear panel flutter. In the passive suppression scheme, a shunt circuit which consists of inductor-resistor is used to increase damping of the system and as a result the flutter can be attenuated. A passive damping technology, which is believed to be more robust suppression system in practical operation, requires very little or no electrical power and additional apparatuses such as sensor system and controller are not needed. To achieve the great actuating force/damping effect, the optimal shape and location of the actuators are determined by using genetic algorithms. The governing equations are derived by using extended Hamilton's principle. They are based on the nonlinear von Karman strain-displacement relationship for the panel structure and quasi-steady first-order piston theory for the supersonic airflow. The discretized finite element equations are obtained by using 4-node conforming plate element. A modal reduction is performed to the finite element equations in order to suppress the panel flutter effectively and nonlinear-coupled modal equations are obtained. Numerical suppression results, which are based on the reduced nonlinear modal equations, are presented in time domain by using Newmark nonlinear time integration method.

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Development and Verification of the Automated Cow-Feeding System Driven by AGV (무인이송로봇기반 자동 소사료 공급 시스템 개발 및 검증)

  • Ahn, Sung-Su;Lee, Yong-Chan;Yoo, Ji-Hun;Lee, Yun-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.18 no.3
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    • pp.232-241
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    • 2017
  • This paper presents an automated cow-feeding system based on an AGV and screw conveyor for domestic livestock farms, which are becoming larger and more commercialized. The system includes a hopper module for loading pellet-type mixed feed at the top of the system, a transfer module mounted with a screw conveyor to transfer feed from the hopper module to the outlet module, an outlet module composed of belt conveyors, and an electromagnetic guided driving-type AGV. The weight of the loaded feed is measured by a load cell located under the transfer module. The system reads the feed discharge information stored in RFID tags installed in each cowshed cell, and a predetermined amount of feed is discharged while the AGV is moving. A cow-feed test system was constructed to determine the design parameters of the screw conveyor in the transfer module that determine the feeding capacity. These parameters include the screw's outer diameter, the screw shaft outer diameter, and screw pitch. The parameters were applied to the finalized cow-feed system construction. A DSP-based main controller and cow-feeding algorithm for different scenarios were also developed to control the system. Experimental results confirmed that the system could supply a total of 21 kg of feed uniformly at 420 g/s for a cowshed cell which has 7 cows. The driving distance was 5 m and the speed was 0.1 m/s. Thus, the proposed system could be applied to standardized domestic livestock farms.

An Emulation System for Efficient Verification of ASIC Design (ASIC 설계의 효과적인 검증을 위한 에뮬레이션 시스템)

  • 유광기;정정화
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.10
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    • pp.17-28
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    • 1999
  • In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

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Theory of efficient array observations of microtremors with special reference to the SPAC method (SPAC 방법에 근거한 상시진동의 효과적 배열 관측 이론)

  • Okada, Hiroshi
    • Geophysics and Geophysical Exploration
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    • v.9 no.1
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    • pp.73-85
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    • 2006
  • Array observations of the vertical component of microtremors are frequently conducted to estimate a subsurface layered-earth structure on the assumption that microtremors consist predominantly of the fundamental mode Rayleigh waves. As a useful tool in the data collection, processing and analysis, the spatial autocorrelation (SPAC) method is widely used, which in practice requires a circle array consisting of M circumferential stations and one centre station (called "M-station circle array", where M is the number of stations). The present paper considers the minimum number of stations required for a circle array for efficient data collection in terms of analytical efficacy and field effort. This study first rearranges the theoretical background of the SPAC algorithm, in which the SPAC coefficient for a circle array with M infinite is solely expressed as the Bessel function, $J_0(rk)$ (r is the radius and k the wavenumber). Secondly, the SPAC coefficient including error terms independent of the microtremor energy field for an M-station circle array is analytically derived within a constraint for the wave direction across the array, and is numerically evaluated in respect of these error terms. The main results of the evaluation are: 1) that the 3-station circle array when compared with other 4-, 5-, and 9-station arrays is the most efficient and favourable for observation of microtremors if the SPAC coefficients are used up to a frequency at which the coefficient takes the first minimum value, and 2) that the Nyquist wavenumber is the most influential factor that determines the upper limit of the frequency range up to which the valid SPAC coefficient can be estimated.

A New Clock Routing Algorithm for High Performance ICs (고성능 집적회로 설계를 위한 새로운 클락 배선)

  • 유광기;정정화
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.11
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    • pp.64-74
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    • 1999
  • A new clock skew optimization for clock routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevent the total wire length from increasing. As the clock skew is the major constraint for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization can increase total wire length, therefore clock routing is performed within the given skew bound which can not induce the malfunction. Clock routing under the specified skew bound can decrease total wire length Not only total wire length and delay time minimization algorithm using merging point relocation method but also clock skew reduction algorithm using link-edge insertion technique between two nodes whose delay difference is large is proposed. The proposed algorithm construct a new clock routing topology which is generalized graph model while previous methods uses only tree-structured routing topology. A new cost function is designed in order to select two nodes which constitute link-edge. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance difference is short. Furthermore, routing topology construction and wire sizing algorithm is developed to reduce clock delay. The proposed algorithm is implemented in C programming language. From the experimental results, we can get the delay reduction under the given skew bound.

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An Implementation of Low Power MAC using Improvement of Multiply/Subtract Operation Method and PTL Circuit Design Methodology (승/감산 연산방법의 개선 및 PTL회로설계 기법을 이용한 저전력 MAC의 구현)

  • Sim, Gi-Hak;O, Ik-Gyun;Hong, Sang-Min;Yu, Beom-Seon;Lee, Gi-Yeong;Jo, Tae-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.4
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    • pp.60-70
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    • 2000
  • An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4:2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.

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수학적 모폴로지의 경계치 변화에 의한 도시환경 지형지물 추출 및 분리응용

  • O, Se-Gyeong;Lee, Gi-Won
    • 한국공간정보시스템학회:학술대회논문집
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    • 2004.12a
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    • pp.139-143
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    • 2004
  • 최근 고 해상도 위성영상정보의 민간 활용에 대한 수요가 증가하면서 기존의 공간 정보를 다루는 여러 응용분야에서 이에 관련된 많은 연구를 하고 있다. 도시교통 환경 분석을 위하여 위성영상정보를 처리하는 과정에 있어서 도로, 건물, 기타 선 구조와 같은 지형지물을 분석하는 과정은 사용자에 따라 주관적일 수 있다. 이러한 배경에서 수학적 그레이 레벨 모폴로지는 하나의 효과적인 접근으로 간주된다. 본 연구에서 지형지물 추출을 위해 윈도우 운영체제에서 실행되는 실질적인 응용 프로그램을 구현하였다. 이 프로그램에서 주요한 지형지물은 그레이 레벨 영상을 이용하여 개방(opening), 폐쇄(closing), 침식(erosion), 팽창(dilation)의 순차적 처리를 통하여 자동적으로 추출된다. 결과적으로, GDPA, 허프 변환 또는 다른 알고리듬들과 비교시 하나의 이점이 된다. 모폴로지 처리와 같이 본 프로그램은 그레이 레벨 값의 범위에 기반하여 지형지물을 추출을 위한 density slicing 기능 또는 주어진 경계치 보다 작은 화소 군집을 제거하는 처리인 'sieve filtering'을 제공한다. 이러한 기능들은 형태학적으로 처리된 결과를 증대하고 지형지물 종류들을 분리하는데 유용하다. 또한 배경의 제거, 잡음 탐지, 도시 환경 원격 탐사에서의 지형지물 특성화에 기여한다. 본 프로그램을 이용하는데 있어서 IKONOS 위성영상을 이용하여 시험 구현하였다. 결과, 다중 경계치 또는 steve filtering을 이용한 그레이 레벨 모폴로지 처리는 복잡한 지형지물과 많은 데이터로 구성된 고해상도 영상 내의 주어진 대상에서 자동적인 처리와 사용자 정의 sieve filtering으로 인한 효과적인 지형지물 추출 방법으로 간주 된다. 시안을 작성 표준화를 위한 첫 단계 시도를 소개하였다.분석 결과는 문장, 그림 및 도표, 장 끝의 질문, 학생의 학습 활동 수 등이 $0.4{\sim}1.5$ 사이의 값으로 학생 참여를 적절히 유도하는 발견 지향적 인 것으로 조사되었다. 그러나 장의 요약은 본문 내용을 반복하는 내용으로 구성되었다. 이와 같이 공통과학 과목은 새로운 현대 사회에 부응하는 교과 목표와 체계를 지향하고 있지만 아직도 통합과학으로서의 내용과 체계를 완전히 갖추고 있지 못할 뿐만 아니라 현재 사용되고 있는 7종의 교과서가 교육 목표를 충분히 반영하지 못하고 있다. 따라서 교사의 역할이 더욱더 중요하게 되었다.괴리가 작아진다. 이 결과에 따르면 위탁증거금의 징수는 그 제도의 취지에 부합되고 있다. 다만 제도운용상의 이유이거나 혹은 우리나라 주식시장의 투자자들이 비합리적인 투자형태를 보임에 따라 그 정책적 효과는 때로 역기능적인 결과로 초래하였다. 그럼에도 불구하고 이 연구결과를 통하여 최소한 주식시장(株式市場)에서 위탁증거금제도는 그 제도적 의의가 여전히 있다는 사실이 확인되었다. 또한 우리나라 주식시장에서 통상 과열투기 행위가 빈번히 일어나 주식시장을 교란시킴으로써 건전한 투자풍토조성에 저해된다는 저간의 우려가 매우 커왔으나 표본 기간동안에 대하여 실증분석을 한 결과 주식시장 전체적으로 볼 때 주가변동율(株價變動率), 특히 초과주가변동율(超過株價變動率)에 미치는 영향이 그다지 심각한 정도는 아니었으며 오히려 우리나라의 주식시장은 미국시장에 비해 주가가 비교적 안정적인 수준을 유지해 왔다고 볼 수 있다.36.4%)와 외식을 선호(29.1%)${\lrcorner}$ 하기 때문에 패스트푸드를 이용하게 된 것으로 응답 하였으며,

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