• Title/Summary/Keyword: 위상검출

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Anti-islanding Detection Method for BESS Based on 3 Phase Inverter Using Negative-Sequence Current Injection (역상분 전류 주입을 적용한 3상 인버터 기반 BESS의 단독 운전 검출 방법)

  • Kim, Hyun-Jun;Shin, Eun-Suk;Yu, Seung-Yeong;Han, Byung-Moon
    • Proceedings of the KIPE Conference
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    • 2015.07a
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    • pp.291-292
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    • 2015
  • 본 논문은 계통과 연계된 3상 전압원 인버터를 기반으로 한 BESS의 능동 단독 운전 검출 방법을 제안한다. 계통 전압의 불평형에서도 안정적으로 위상을 추종할 수 있는 DDSRF_PLL(Decoupled Double Synchronous Reference Frame_PLL)방식을 적용 하였으며, 검출된 위상각 정보를 통해 정상분 전류 제어기와 역상분 전류 제어기를 독립적으로 제어할 수 있게 된다. 이를 위해 IEEE 1547과 UL1741에서 제시하는 단독 운전 기준 시험 회로를 구성하여 PSCAD/EMTDC 소프트웨어를 통한 시뮬레이션과 5kw프로토타입 하드웨어 장치를 통해 제안된 단독 운전 검출 방법을 검증하였다.

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Color enhancement system Based on the improvement of Transition Time and color detdetion Stability (천이 시간 개선과 색검출 안정화 기반의 색 향상 시스템)

  • Lee, Eung-Joo
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.3
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    • pp.715-719
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    • 1998
  • In this paper, we propose a color enhancement system which is based on the improvement of transition time problem and specific color detection stability. The proposcd system apply the time difference correction step to corrects time difference which is taken place at the transimission process between color signal and color subcarrier signal and to reduce detection errors. And also, we proposed stability method to improve transition time problem and detection efficiency as the control of reference color. The proposed system controls specific color when the mean difference value of detected voltages greater than the value of minimum discriminate voltages of two adjacent color signals. Thus, the color enhancement system improves detection efficiency and controls specific color from the color signal without overlapping of correction range.

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A Multiple Gain Controlled Digital Phase and Frequency Detector for Fast Lock-Time (빠른 Lock-Time을 위한 다중 이득 제어 디지털 위상 주파수 검출기)

  • Hong, Jong-Phil
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.2
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    • pp.46-52
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    • 2014
  • This paper presents a multiple gain controlled digital phase and frequency detector with a fast lock-time. Lock-time of the digital PLL can be significantly reduced by applying proposed adaptive gain control technique. A loop gain of the proposed digital PLL is controlled by three conditions that are very large phase difference between reference and feedback signal, small phase difference and before lock-state, and after lock-state. The simulation result shows that lock-time of the proposed multiple gain controlled digital PLL is 100 times faster than that of the conventional structure with unit gain mode.

A Study on the Phase Locked Loop Macromodel for PSPICE (PSPICE에 사용되는 위상동기루프 매크로모델에 관한 연구)

  • 김경월;김학선;홍신남;이형재
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.9
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    • pp.1692-1701
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    • 1994
  • Macromodeling technology is useful to simulate and analyze the performance of new elements and complicated circuits or systems without any changes in today's general simulator, PSPICE. In this paper, Phase Locked Loop(PLL) is designed using macromodeling technique. The PLL macromodel has two basic sub-macromodels of the phase detector and the voltage controlled oscillator(VCO). The PLL macromodel has two open terminals for inserting RC low pass filter. The PLL macromodel is simulated using simulation parameters of LM565CN manufactured in the National company. At a free-running frequency, 2500Hz, upper lock range and lower capture range was 437Hz, 563Hz, respectively. Also, experimental results and simulation results of LM565CN PLL show good agreement.

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A Frequency Locked Loop Using a Phase Frequency Detector (위상주파수 검출기를 이용한 주파수 잠금회로)

  • Im, Pyung-Soon;Lee, Dong-Hyun;Yeom, Kyung-Whan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.7
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    • pp.540-549
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    • 2017
  • A phase frequency detector(PFD) composed of logic circuits is widely used in a phase locked loop(PLL) due to the easy implementation for integrated circuits. A frequency locked loop(FLL) removes the reference oscillator in the PLL, and the resonator serves as a reference oscillator. A frequency detector(FD) is indispensable for the FLL configuration, and a FD, which is usually composed of a mixer is used to build an FLL. In this paper, instead of FD using mixer, a FD is constructed by using 1.175 GHz resonator composed of microstrip and PFD taking the versatility of PFD into consideration. Using the designed FD, FLL oscillating at a frequency of 1.175 GHz is composed. As a result of comparison with the FLL composed of FD using mixer, it was confirmed that the proposed FLL has better phase noise performance than FLL using mixer FD with FLL bandwidth.

Modeling and Application Research of Zero Crossing Detection Circuit (Zero Crossing Detection 회로 Modeling 및 응용연구)

  • Jeong, Sungin
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.4
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    • pp.143-148
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    • 2020
  • In the case of a system that detects and controls the phase of an alternating voltage, the analog control method compensates the phase offset part by filtering for the detected phase and applies it to the control. However, in the digital control method, precise control cannot be achieved due to an error between the operating frequency of the microprocessor or the microcontroller and the input phase time when controlled using such phase detection. In general, when the method used is a certain time, the accumulated error is compensated and adjusted at random. To solve this problem, a method of detecting a zero point in real time and compensating for the operating frequency of the microprocessor is needed. Therefore, the research to be performed in this paper to reduce these errors and apply them to precise digital control is as follows. 1) Research on how to implement Zero Crossing Detection algorithm through simulation modeling to compensate the zero point to match the operating frequency through detection. 2) A study on the method of detecting zero points in real time through the Zero Crossing Detection design using a microcontroller and compensating for the operating frequency of the microprocessor. 3) A study on the estimation of the rotor position of BLDC motors using the Zero Crossing Detection circuit.

Frequency modulation spectroscopy of a super-cavity using a single mode He-Ne laser (단일모드 헬륨네온레이저를 사용한 초공진기의 주파수 변조 분광연구)

  • 서호성;윤태현;조재흥;정명세;류갑열;김영덕;최옥식
    • Korean Journal of Optics and Photonics
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    • v.3 no.1
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    • pp.27-36
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    • 1992
  • Frequency modulation spectroscopy of the super-cavity, of which finesse is app. 40,000 has been demonstrated by using a sigle mode He-Ne laser. In-phase and quardrature components of frequency modulation signals (FM signal) were obtained by using the 1.5 MHz-driven-electrooptic phase modulator. The vector locus of the FM signa in the phase space, which is consisted of in-phase and quardrature components of the FM signal, was observed and analyzed for the dependence of FM signal upon the phase of the reference signal of a phase-sensitive-detector. According to rotating the phase of the reference signal, the vector locus was observed to rotate with the same phase angle as the reference signal. The in-phase component of the FM signals will be used to stabilize the frequency of the He-Ne laser to the resonant frequency of the super-cavity.

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Suppression Circuit Design of interference Using Orthogonal Signal (직교신호를 이용한 간섭 억제회로 설계)

  • Yoon, Jeoung-Sig;Chong, Jong-Wha
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.10A
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    • pp.969-979
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    • 2002
  • This paper proposes an novel method of minimizing Interference which causes data decision error in digital wireless communications. In this method, in order to suppress ISI which is caused by the phase difference between the transmitted and received signal phases, the transmitted and received signals are always kept orthogonal by compensating the transmitted signal for detecting the phase noise and the delay of the received signal was implemented by MOS circuits. To delay the phase of the signal, additive white Gaussian noise (AWGN) environment was used. The phase and delay of the signal transmitted through AWGN channel were compensated in the modulator of the transmitter and the compensated signal was demodulated using quasi-direct conversion receiver and QPSK demodulator. ISI suppression was achieved by keeping the orthogonality between the compensated transmitted signal and the receive signal. The error probability of data decision was compared. By simulation the proposed system was proved to be effective in minimizing the ISI.

Sampling Phase Detector for NRZ Random Bit Synchronization (NRZ Random Bit 동기를 위한 표본 위상 검출기)

  • 박세현;박세훈
    • Journal of Korea Multimedia Society
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    • v.3 no.6
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    • pp.652-660
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    • 2000
  • This paper proposes a new type of sampling Phase Detector (SPD) for NRZ random bit synchronization circuit. The proposed SPD calculates the mean value of phase difference between bit interval of input signal and period of local reference. Simulated and experimental results show that the proposed SPD is applicable to the phase detector for NRZ random signal. finally the Random NRZ bit synchronization circuit. is designed and implemented by using SPD.

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Phase Modulation Optical Delay Line for Ultrafast OCT Application (초고속 OCT응용을 위한 위상변조 광지연단)

  • Hwang Daeseo;Lee Young-Woo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.4
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    • pp.861-864
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    • 2005
  • In this paper, we system the system design and numerical analysis of the ultrafast optical delay line using by optical phase modulator. The numerical analysis carried out with 1310nm, lops laser and electro-optic phase modulator. As the results of numerical analysis, we show a scanning rate of 0.5 GHz and a delay range of 19.0ps. Compare with mechanical delay line, the optical delay line has a high scanning speed and a high repetition rate.