• The Journal of the Korea Contents Association
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• v.2 no.3
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• pp.80-86
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• 2002

In this paper, we propose the new optical security technique using two phase holograms based on interferometer. The encoded random phase image does not have any information on the original image. Without Hewing the key mask, one cannot decode the encrypted image and regenerate the original image. And the use of two phase only images in the proposed security system leads to maximum optical efficiency (100% in theory). Also they cannot be detected by an intensity detector such as a CCD camera. Computer simulations and optical experiments show performance of the proposed methods.

• Korean Journal of Optics and Photonics
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• v.23 no.1
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• pp.23-31
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• 2012

In this paper, we developed a frequency-domain diffuse optical imaging (DOI) system for imaging non-invasively using near-infrared (NIR) light sources and detectors. 70-MHz modulation and a homodyne scheme were adopted. By calibration of the coupling coefficients, concurrent detection measurements by 4 detector sets were optimized. We presented experimental reconstruction images of absorption and scattering coefficients in a liquid phantom, located an anomaly in the phantom and determined its optical properties. The images by the multi-channel concurrent detection were improved over the results by single-channel sequential detection. Tomographic slices of absorption and scattering coefficients in the phantom with an anomaly were also presented.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.2037-2039
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• 2004

고전압 전력기기분야에 광섬유 전압센서를 적용해보고자하는 연구는 20여년 전부터 꾸준히 진행되어 왔었다. 본 연구에서는 구조가 간편한 광섬유 패브리페로 간섭계를 이용한 고전압기기 적용형 전압센서가 시도되었다. 신호변환은 정전력을 이용하여 전압의 변화를 광섬유스트레인센서로 검출하며, 해상도를 확보하기 위하여 공진기의 길이를 1cm, 위상을 스캐닝하는 변조방법을 적용하였고, 교류전압 1000V까지 적용 타당성을 시험하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.2 no.3
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• pp.20-25
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• 1997

SRM은 많은 장점으로 인해 각종 산업분야에 적용을 검토하고 있다. 그러나 토오크리플과 소음이 교류전동기보다 상대적으로 높은 단점이 있다. SRM은 상전류파형이 동작특성과 토오크리플발생에 큰 영향을 미친다. 본 논문에서는 토오크리플을 줄이고 정밀한 속도제어를 위해 순시도통각제어와 PLK제어시스템을 이용하였다. PLL의 위상검출기는 도통각제어에, 루우프필터의 출력은 순시 인가전압의 제어에 각각 도입하여 속응성을 높이고 토오크리플을 줄일 수 있도록 하였다. 실험을 통하여 정밀한 속도제어와 토오크리플 저감특성을 확인할 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.52-59
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• 1998

New types of PFD (phase-frequency detector) are proposed with reset time and propagation delay reduced. The perfomrance of our proposed PFDs are confirmed by SPICE simulation with 0.8.mu.m CMOS process parameter. As a result of simulation, the reset time of PFDs are 0.32 nsec and 0.030 nsec in capture-process. The proposed PFDs can be used in hihg-speed phase-licked loop (PLL).

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.1
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• pp.31-38
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• 2024

The digital phase-locked loop(DPLL) is one of the circuits composed of a digital detector, digital loop filter, voltage-controlled oscillator, and divider as a fundamental circuit, widely used in many fields such as electrical and circuit fields. A state estimator using various mathematical algorithms is used to improve the performance of a digital phase-locked loop. Traditional state estimators have utilized Kalman filters of infinite impulse response state estimators, and digital phase-locked loops based on infinite impulse response state estimators can cause rapid performance degradation in unexpected situations such as inaccuracies in initial values, model errors, and various disturbances. In this paper, we propose a two-layer Frobenius norm-based finite impulse state estimator to design a new digital phase-locked loop. The proposed state estimator uses the estimated state of the first layer to estimate the state of the first layer with the accumulated measurement value. To verify the robust performance of the new finite impulse response state estimator-based digital phase locked-loop, simulations were performed by comparing it with the infinite impulse response state estimator in situations where noise covariance information was inaccurate.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.8
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• pp.65-74
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• 2005

It is required for getting the ring laser gyro output purely related to the input rotation to eliminate the output of the modulated angular vibration from the ring laser signal. In this paper we discuss the dither stripping methods of compensating the ring laser signal by converting the rate signal of dither detector from voltage to frequency for a dither type ring laser gyro. We discuss the differential methods for getting rid of the offset of the V-F signal. And we develope the methods of compensating the phase differences between the ring laser signals and the V-F differential signals by using analog integrator and digital time delays. And also, we develope the gain calculation method by comparing the standard deviations of the ring laser signals with V-F differential signals. We implemented these methods and analyzed the effectiveness of these methods by comparing the dither trapping methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1242-1249
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• 2012

This paper proposes a metastability-free synchronization method and a mesochronous synchronizer for NoC. It uses the clock transmitted from TX as a strobe and solves the metastability problem by selecting one of rising or falling clock edge depending on the sampling value in RX when the phase difference between clocks is under a metastability window. The logic simulation results show that it works without metastability under $0^{\circ}{\sim}360^{\circ}$ phase difference in the synchronizer that a fault is inserted. The mesochronous synchronizer has a simple control logic and is suitable for NoC.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.247-252
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• 2009

This paper presents an Integer-N phase-locked loop (PLL) frequency synthesizer using a novel prescaler based on a charge pump and clock triggering circuit. A quadrature VCO has been designed for the 900MHz UHF RFID application. In this circuit, a voltage-controlled oscillator(VCO), a novel Prescaler, phase frequency detector(PFD), charge pump(CP), and analog lock detector(ALD) have been integrated with 0.35-${\mu}m$CMOS process. The integer divider has been developed with a verilog-HDL module, and the PLL mixed mode simulation has been performed with Spectre-Verilog co-simulator. The sweep range of VCO is designed from 828 to 960 MHz and the VCO generates four phase quadrature signals. The simulation results show that the phase noise of VCO is -102dBc/Hz at 100 KHz offset frequency, and the maximum lock-in time is about 4us with 32MHz step change (from 896 to 928 MHz).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.10
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• pp.1147-1158
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• 2008

In this paper, we designed a phase-looking circuit that locks the 16.8 GHz VTDRO to a 700 MHz SAW oscillator using SPD as a phase detector Direct phase locking with loop filter alone causes the problem of lock time, so VTDRO is phase leered by loop filter with the aid of time varying square wave current generator. The current generator is related to the loop filter and needs the systematic toning. In this paper, a systematic design of the current generator and loop filter is presented. The fabricated PLDRO shows a stabilized frequency of 16.8 GHz, a output power 6.3 dBm, and a phase noise of -101 dBc/Hz at the 100 kHz offset.