• Proceedings of the KIPE Conference
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• 2010.11a
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• pp.286-287
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• 2010

계통연계 인버터 제어 시 계통 전압과 동상인 전류를 공급해 주기 위해 반드시 계통 전압의 위상 정보가 필요하다. 기존의 PLL 방법은 계통 전압에 고조파가 존재하지 않을 시에 검출된 위상 값은 정확하지만, 고조파 존재 시 정확한 위상 값을 얻을수 없다. 본 논문에서는 전차원 상태 관측기를 이용하여 기본파 성분과 고조파 성분을 분리하여 검출된 위상의 정상상태 오차를 감소시킬 수 있고, 저역통과필터를 고려한 PLL 시스템의 모델링을 이용하여 동특성을 개선하는 방법을 제안하였다. 이를 모의실험을 통하여 검증하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.967-973
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• 2009

In this paper, X-band satellite communication oscillator of double phase locked is implemented by constructing a couple of phased-locked loop, and then we have analyzed the phase noise of designed PLL-DRO. The designed phase-locked oscillator is consist of series feedback DRO, frequency divider, phase detector, loop filter and programmable PLL-IC. By dividing oscillation frequency of 12.6 GHz into two frequencies, it exhibits output power of 15.32 dBm at 6.3 GHz. Phase noises of implemented oscillator are -81 dBc/Hz@100Hz, -100.86 dBc/Hz@1 kHz, -111.12 dBc/Hz@10 kHz, -116 dBc/Hz@100 kHz and -140.49 dBc/Hz@1 MHz respectively. These indicate excellent stable operation of oscillator and very good phase noise characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.217-221
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• 2000

In this paper, we analyze the effect of phase noise from PLL frequency synthesizer on 64QAM when detecting the corrupted signals. To predict the phase noise of oscillator very accurately, we considered that oscillator has the linearly time-varying nature when the input impulsive torrent to oscillator is small. The performance which detects the corrupted signal by oscillator phase noise is compared with only affected by AWCN and then analyze how much it degrade system performance for 64QAM.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• Korean Journal of Optics and Photonics
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• v.8 no.5
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• pp.426-430
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• 1997

A signal processor is implemented to verify the possibility of a closed-loop signal processing for the open-loop fiber-optic gyroscope (FOG). As an all-digital implementation of phase tracking scheme, it does analog-to digital conversion of the detector output and signal processing all-digitally thereafter for a noise-immune FOG signal processor. It has a potential of 36-bits resolution in the $2\pi$ range which is best in the number and sets no limit in the magnitude of the phase shift. The new signal processor was tested on an all-fiber gyroscope and turned out to have a resolution of $3\mu$rad(corresponds to 0.74 deg/hr), which is good enough to measure the Earth's rotation rate.

• Journal of Navigation and Port Research
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• v.26 no.1
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• pp.127-136
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• 2002

This paper Presents a discussion on the design and realization for the Phase Sensitive Defector (PSD) circuitry of Flu$\chi$-gate Compass that gives direction information to the Directional Frequency Analysis and Recording (DIFAR) Sonobuoy in Air Anti-Submarine Warfare. PSD circuitry is realized with Twin-T RC networked active band-pass filter. Results of a performance test the PSD circuitry shows that the effectiveness of band-pass filtering of desired $2F_0$ second harmonic signal, which is Pro- portional to the direction of earth's magnetic field. This resulted in the extraction of direction information.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.7
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• pp.573-581
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• 2014

We proposed a hopping phase estimator to demodulate the received signals without any hopping information in frequency hopping spread spectrum systems. The demodulation process in this paper is as follows: hopped frequency tracking is accomplished by choosing a frequency component with maximum amplitude after taking discrete Fourier transform and a hopping frequency estimator which estimates the phase generated by hopped frequency is established through difference product and down-sampling. We obtained the probability density function and variance performance of the proposed estimator and confirmed that the analysis and the simulation results were agreed with each other.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.581-584
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• 2003

It is important to know phase offsets of PN (Pseudo Noise) sequences in spread spectrum communications since the acquisition is equivalent to make a phase offset between a receiving PN sequence and a PN sequence of local PN generator be identical. In this paper, a phase offset enumeration method for PN sequences with error detection, and its application to the synchronization are proposed. The phase offset enumeration far an n-tuple PN sequence and its error detection are performed when one period of the sequence is received. Once the phase offset of the receiving sequence is calculated, we can easily accomplish the synchronization by initializing shift registers of a local PN generator according to the phase offset value. The mean acquisition time of the proposed synchronization method is derived analytically, and we see that the method acquires very fast acquisition in the high SNR (Signal-to- Noise Ratio) environment.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.11
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• pp.842-850
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• 2018

In this paper, the design and fabrication of a frequency-locked-loop(FLL) 5-GHz oscillator with a single resonator is presented. The proposed oscillator is the simplified version of the previous FLL oscillator with two separate resonators in the VCO and frequency detector. The resonator is commonly used in the VCO and frequency detector of the proposed oscillator configuration. The 5-GHz oscillator is implemented on the hetero-multilayer substrate composed of a Rogers' RO4350B laminate, which has excellent high-frequency performance, and the commercial FR4 three-layer substrate. The frequency locking occurs at approximately 5 GHz and has an output power of 3.8 dBm. The phase noise has a free-run VCO phase noise at frequencies above 1 kHz, and an FLL background noise at frequencies below 1 kHz. For this loop-filter, the phase noise showed an improvement of approximately 12 dB at the offset-frequency of 100 Hz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.7
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• pp.661-668
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• 2004

A novel method to reject the spurious signals which are occurred at Weaver-type low-IF transmitter was proposed in this paper. The spurious signals are generated by the gain and phase imbalances of I/Q channel or imperfect characteristics of 90$^{\circ}$ phase shifter in local oscillator for I/Q channel source. By deriving the gain and phase-based functions from RF spurious signal with the channel imbalance information, the lie channel imbalances were deduced as functions with magnitude and sign dependent on I/Q channel imbalance degree. The proposed method compensates the estimated I/Q channel imbalances by correlation values between the down-converted signal obtained by squaring the output signal itself using a simple mixer and the modified baseband signal. By comparing two signals after A/D conversion, the magnitude and sign of each type of imbalances can be determined separately and simultaneously. Based on the I/Q channel imbalance compensation, the spurious signals can be reduced by adjusting the gain and phase values of I or Q channel signal. The way to estimate the channel imbalances of the up-conversion mixer was presented and verified by using theoretical derivations and computer simulations.