• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.5
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• pp.218-223
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• 2001

The chemical-mechanical polishing process was carried out for 2"-dia. sapphire wafer grown by horizontalBridgman method on the urethane lapping pad with the silica sol. The polished wafer shows the full-width at halfmaximum of 200~400 arcsec in double-crystal X-ray diffraction, indicating that the slicing, grinding and lapping processes before the polishing process affected the crystalline structural property of the wafer surface by the mechanical residual stress. For the inclusion of surface treatments after chemical-mechanical polishing such as the thermal annealing at the temperature of $1,200^{\circ}C$for 4 hrs. and chemical etching, the crystalline quality was sigdicantly enhanced with the reduced full-width at half maximum up to 8.3 arcsec.arcsec.

• Korean Journal of Crystallography
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• v.12 no.3
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• pp.177-181
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• 2001

We have studied superhydrophilic properties of TiO₂thin films in relation with those crystal structures due to the heat treatments. Thin films were fabricated on Si (100) wafers using a conventional Sol-Gel method. Following drying and sintering processes, TiO₂film had an anatase phase with additional heat treatment at 500℃, an rutile phase at 1000℃, and a mixture of anatase and rutile phase at 750℃. All these films got hydrophilic even without any UV illumination. Especially the sample treated at 750℃ had a superhydrophilic contact angle of 5°. We suggested that the superhydrophilic films should have a mixture of anatase and rutile phase for the best performance. The hydrophilic TiO₂films were slowly degraded into the hydrophobic state in the dark room but quickly recovered back with les than 1 hour of UV illumination.

• Journal of the Korean Society for Nondestructive Testing
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• v.32 no.2
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• pp.142-148
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• 2012

This study presents the assessment results of adhesive properties on the interface between a silicon wafer and nano-scale polymer thin film pattern through UAFM images by using the contact resonance frequency of the cantilever. For the experiment, we varied surface treatment processes for the silicon wafer and fabricated a 300nm polymer thin film pattern through lithography. Images from the optical microscope were used to compare the produced test specimens for adhesive condition and the critical load value from the nano scratch test was used to verify the adhesive condition of the nano pattern. Each test specimen resulted in a $1{\mu}m{\times}1{\mu}m$ surface image and subsurface adhesive image. Adhesive condition was evaluated by image contrast differences on the interface according to the changing amplitudes and phases of contact resonance frequency.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.97-97
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• 2010

많은 플라즈마 공정 중에 건식 식각은 복잡하고 표면반응이 잘 알려지지 않은 등의 이유로 가장 어려운 분야 중의 하나이다. 이러한 이유로 식각 장치 디자인뿐만 아니라 플라즈마를 이용한 건식 식각의 공정 조건은 수많은 시행착오를 통해 시도되어 왔다. 이런 문제들을 극복하기 위해 많은 연구자들에 의해서 다양한 방법과 tool을 이용해 모델링이 시도되고 있다. 본 연구에서는 $CF_4$ 가스를 이용한 유도결합 플라즈마에 의해 Si와 $SiO_2$를 식각하는 것을 상용 프로그램인 전산모사 유체역학 시뮬레이터인 CFD-ACE+를 이용하여 모델링했다. 150 mm 직경의 웨이퍼에 대한 모델은 식각 속도 실험결과와 비교 하였다. Ar의 경우 20 mTorr에서 13.56 MHz, 500 W인가 시 2.0 eV의 전자온도와 $7.3{\times}10^{11}\;cm^{-3}$의 전자밀도가 계산결과와 상당히 일치하게 측정되었고, $CF_4$를 이용한 $SiO_2$ 식각에서도 식각 속도가 평균 190 nm/min로 일치했고 식각 균일도는 3% 였다. 450 mm 웨이퍼 공정용 장치의 모델 계산 결과에서는 안테나와 기판의 거리, 챔버의 단면적, 기판 지지대와 배기구와의 높이 등 기하학적인 구조와 각 안테나 턴의 위치 및 전류비가 플라즈마 균일도에 많은 영향을 주었으며, 안쪽부터 4 turn이 있는 경우 2번째, 4번째 turn에만 1:4의 전류비를 인가했을 때, 수십%의 전자밀도의 불균일도를 4.7%까지 낮출 수 있었다. 또한, Si 식각에서는 식각 속도의 분포가 F radical의 분포와 같은 경향을 보임을 확인했고, $SiO_2$ 식각에서는 전자 밀도의 분포와 일치함을 확인함으로써 균일한 식각을 위해서 두 물질의 식각 공정에서는 다른 접근의 시도가 필요함을 확인했다. 플라즈마의 준중성 조건을 이용해서 Poisson 방정식을 풀지 않고 sheath를 해석적 모델로 처리하는 방법과, Poisson 식으로 정전기장을 푸는 방법을 통해서 입사 이온의 에너지 분포를 비교하였다. 에너지 범위는 80~120 eV로 같지만, 실험에서는 IED가 낮은 에너지 쪽이 더 높게 측정됐고, 계산 결과에서는 높은 에너지 쪽이 높았다.

• Journal of the Korean Vacuum Society
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• v.19 no.2
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• pp.96-104
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• 2010

We suggest here a cost-effective replica fabrication method for transparent and hard molds for imprinting lithography such as NIL and S-FIL. The process starts with the use of a replica hard mold from a master, using a polymer copy as a carrier. The polymer copy as a carrier was treated by soluble process for forming anti-adhesion layer. Duplicated hard molds can eliminate direct contact between a hard master and a patterned polymer on a substrate and the generated contamination of a master during the imprinting process. The replica hard mold exhibits the glass-like properties introduced here, such as transparency and hardness, make it appropriate for nanoimprint lithography and step-and-flash imprint lithography.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.655-655
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• 2013

그래핀은 높은 전자 이동도, 열전도도, 기계적 강도, 유연성 등의 고유한 특성으로 다양한 분야에 응용하기 위한 연구가 수행되고 있으며, 특히 전자 소자에의 적용에 관한 연구가 활발히 이루어지고 있다. 전자 소자에 적용하기 위해서는 성장 및 물성에 관한 규명, 응용 소자에 따른 특성 평가가 필요하다. 이러한 소자 특성은 그래핀 물성에 의한 영향이 기본적이지만 에칭, 전사 등의 공정 중 발생하는 오염, 표면 특성, 잔여물 등에 의한 물성 변화 또한 분석 및 제어에 관한 연구가 필요하다. 열화학증착법(thermal chemical vapor deposition)을 이용한 그래핀 합성은 구리 기판을 사용하며, 합성된 그래핀의 에칭, 박리 및 전사 공정이 있다. 이러한 공정 중 발생하는 오염 입자가 그래핀 표면에 흡착되거나, 제거되지 않은 PMMA 잔여물이 그래핀의 특성에 영향을 미치게 된다. 따라서 본 연구에서는 $CO_2$ 클러스터의 표면 충돌을 이용하여 이러한 오염 물질 및 잔여물을 제거하고 그래핀 표면을 평탄화하는 것에 관한 연구를 수행하였다. 가스 클러스터란 작동기체의 분자가 수십에서 수백 개 뭉쳐 있는 형태를 뜻하며 이렇게 형성된 클러스터는 수 nm 크기를 형성하게 된다. 그리고 짧은 시간의 응축에 의해 수십 nm 크기 까지 성장 하게 된다. 클러스터를 이용한 표면 처리는 충돌에 의한 제거에 기반 한다. 따라서 생성 및 가속되는 클러스터로부터 대상으로 전달되는 운동량의 정도가 세정 특성에 영향을 미치며 이는 생성되는 클러스터의 크기에 종속적이다. 생성 클러스터의 크기 분포는 분사거리, 유량, 분사 각도, 노즐 냉각 온도 등의 변수에 관한 함수이다. 본 연구에서는 이러한 변수들을 제어하여 클러스터를 이용한 그래핀 표면 처리 실험을 수행하였다. 평가는 클러스터 표면 처리 전과 후의 특성 비교에 기반 하였으며, 광학 현미경을 이용한 표면 형상 측정, 라만분광 분석, AFM을 이용한 표면 조도 측정, 그래핀 면저항 측정 결과를 비교하였다. 평가 결과를 통하여 표면 처리를 하지 않은 그래핀에 비하여 면저항과 표면 조도가 낮아지는 것을 확인 할 수 있었다. 또한 클러스터 세정은 300 mm 웨이퍼 크기 이상의 대면적을 짧은 시간에 건식으로 세정할 수 있다는 장점이 있어 향후 최적화를 통해 그래핀 양산 시 특성 향상을 위한 후처리 방법으로 사용될 수 있음을 확인하였다.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.91-96
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• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

• Korean Journal of Materials Research
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• v.8 no.6
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• pp.532-537
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• 1998

The purpose of this study was to investigate the behavior of ozone in DI water and the reaction with wafers during the semiconductor wet cleaning process. The solubility of ozone in DI water was not only dependent on the temperature but also directly proportional to the input concentration of ozone. The lower the initial ozone concentration and the temperature, the longer the half-life time of ozone. The reaction order of ozone in DI water was calculated to be around 1.5. The redox potential reached a saturation value in 5min and slightly increased as the input ozone concentrations increased. The completely hydrophilic surface was created in Imin when HF etched silicon wafer was cleaned in ozonized DI water containing higher ozone concentrations than 2ppm. Spectroscopic ellipsometry measurements showed that the chemical oxide formed by ozonized DI water was measured to be thicker than that by piranha solution. The wafers contaminated with a non-ionic surfactant were more effectively cleaned in ozonized DI water than in piranha and ozonized piranha solutions.

• Clean Technology
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• v.22 no.4
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• pp.274-280
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• 2016

In this study, it was to develop a chemical method that can recycle the cutting oil which accounts for about 25% of the cost of the process among containing materials of silicon waste sludge generated in the process for producing a solar cell wafer. The 7 types of reagents have been used, including acetone, HCl, NaOH, KOH, $Na_2CO_3$, HF, $CH_2Cl_2$, etc. for this experiment. And It was carried out at a speed of 3000 rpm for 60 minutes centrifugation after performing a reaction with a waste sludge at various concentrations. As a result, the best reagents and conditions for separating the solid such as a silicon powder and a metal powder and liquid cutting oil were identified as 0.3 N NaOH. It is found to be pH 6.05 in a post-processing recycled cutting oil with 0.3 N NaOH after reaction of waste sludge and 0.1 N HCl which is effective to remove metal powder in order to adjust the pH to suit the properties of the weak acid is a commercially available cutting oil and it showed excellent turbidity than when applied to sludge with 0.3 N NaOH alone. The results of FT-IR analysis which can compare the properties of the commercially available cutting oil shows it has a possibility of recycling oil. The cutting oil recovery rate obtained through the experiment was found to be 86.9%.

• Journal of the Korean Vacuum Society
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• v.20 no.3
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• pp.225-232
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• 2011

Reactive ion etching (RIE) technique for maskless surface texturing of mc-silicon solar wafers has been applied and succeed in fabricating a grass-like black-silicon with an average reflectance of $4{\pm}1%$ in a wavelength range of 300~1,200 nm. In order to investigate the optimized texturing conditions for mass production of high quantum efficiency solar cell Surface characteristics such as the spatial distribution of average reflectance, micrscopic surface morphology and minority carrier lifetime were monitored for samples from saw-damaged $15.6{\times}15.6\;cm^2$ bare wafer to key-processed wafers as well as the mc-Si solar cells. We observed that RIE textured wafers reveal lower average reflectance along from center to edges by 1% and referred the origin to the non-uniform surface structures with a depth of 2 times deeper and half-maximum width of 3 times. Samples with anti-reflection coating after forming emitter layer also revealed longer minority carrier lifetime by 40% for the edge compared to wafer center due to size effects. As results, mc-Si solar cells with RIE-textured surface also revealed higher efficiency by 2% and better external quantum efficiency by 15% for edge positions with higher height.