• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.548-548
• /
• 2013

태양전지 제작에서 도핑 공정은 실리콘 웨이퍼에 불순물 원자를 주입시켜 p-n 접합을 형성시키는 과정이다. 도핑 공정은 주로 3족 혹은 5족 원소를 사용한다. 기존의 도핑 공정 장치는 소성로 및 레이저 장비를 사용하여 생산단가가 높고, 웨이퍼의 전면 도핑이 힘들다는 단점이 있다. 하지만 플라즈마 제트를 사용한 도핑장치는 저가의 장비를 개발할 수 있고, 전면 도핑이 쉽다는 장점을 가진다. 또한 도핑 농도 및 깊이 조절, 높은 농도의 도핑이 가능하다는 기존 장비의 장점을 유지한다. 플라즈마 제트를 솔라셀 웨이퍼 위에 도포된 dopant material layer에 조사하면 주로 플라즈마와 dopant간의 열적인 반응에 의하여 doping이 된다. 도핑을 위한 플라즈마 제트는 전류량의 조절 및 조사하는 양에 따라서 도핑 온도를 쉽게 조절 가능하다. 본 연구에서는 챔버 내 Ar 가스를 채운 후 플라즈마를 생성시켜 방전 특성을 조사한다. 챔버 내 가스의 압력, 전극과의 거리, 전극의 형태 등 장치의 조건을 변화시켜 특성을 확인하고, 안정적인 플라즈마의 물성을 유지하기 위한 조건을 찾는다. 또한 일반 대기압에서 가스 유량변화, 전극과의 거리, 전극의 형태 등 조건에 따른 방전 특성 및 플라즈마 방출 특성을 조사한다.

• Electronics and Telecommunications Trends
• /
• v.13 no.3 s.51
• /
• pp.71-83
• /
• 1998

반도체 제조용 웨이퍼의 온도를 측정하고 제어하는 기술의 진보로 열처리 장비 시장에서 점점 더 각광을 받고 있는 급속 열처리(rapid thermal process: RTP) 장치의 최근 기술 동향을 전반적으로 조사 분석하였다. RTP의 장점, 온도 제어 모델링 기술(model-based control), 최근에 개발된 여러 종류의 RTP 시스템 설계 및 이들 각각의 기술적인 문제들이 기술된다. 새롭게 개발된 단일 wafer furnace와 광자 효과를 이용한 rapid photothermal process (RPP)에 관해서도 기술하였다. 아울러 최근 열처리 장비 업체들의 현황과 열처리 장비 시장의 향후 전망에 관해서도 검토하였다.

• Journal of the Microelectronics and Packaging Society
• /
• v.22 no.3
• /
• pp.31-38
• /
• 2015

In order to achieve a high speed and high quality silicon wafer bonding, the room-temperature direct bonding using atmospheric pressure plasma and sprayed water vapor was developed. Effects of different plasma fabrication parameters, such as flow rate of $N_2$ gas, flow rate of CDA (clear dry air), gap between the plasma head and wafer surface, and plasma applied voltage, on plasma activation were investigated using the measurements of the contact angle. Influences of the annealing temperature and the annealing time on bonding strength were also investigated. The bonding strength of the bonded wafers was measured using a crack opening method. The optimized condition for the highest bonding strength was an annealing temperature of $400^{\circ}C$ and an annealing time of 2 hours. For the plasma activation conditions, the highest bonding strength was achieved at the plasma scan speed of 30 mm/sec and the number of plasma treatment of 4 times. After optimization of the plasma activation conditions and annealing conditions, the direct bonding of the silicon wafers was performed. The infrared transmission image and the cross sectional image of bonded interface indicated that there is no void and defects on the bonded wafers. The bonded wafer exhibited a bonding strength of average $2.3J/m^2$.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.3
• /
• pp.59-65
• /
• 1999

In this paper, we had studied the possibility of application as Cu thin films from (hfac)Cu(VTMOS) which is very stable. Cu thin films had been studied as a function of deposition temperature. Substrates used in the experiment were PVD TiN on Si wafer. Deposition conditions were as follow : deposition temperature $50^{\circ}C$. Cu thin films were analyzed by AES, four point probe, XRD and SEM. All of deposited films were very pure and some favoring of <111> planes perpendicular to the substrate surface were observed. Cu thin films had two distinct growth rates at various deposition temperature. One is the surface reaction limited region below $200^{\circ}C$, and the other is the mass transport limited region above $200^{\circ}C$. The resistivity of deposited Cu thin films under the optimum deposition condition is $2.5mu\Omega.cm$ Thus, properties of deposited Cu thin films using (hfac)Cu(VTMOS) didn't show difference with Cu thin films from other precursors.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.35 no.5
• /
• pp.459-465
• /
• 2011

Excessive heat may be generated during the semiconductor manufacturing process. Therefore, precise control of temperature is required to maintain a constant ambient temperature and wafer temperature in the chamber. Compared to an industrial chiller, a semiconductor chiller's power consumption is high because it is in continuous operation for a year. Because of this high power consumption, it is necessary to develop an energy-efficient chiller by optimizing the operation. The competitiveness of domestic products is low because of the high energy consumption. We experimentally investigated a domestic semiconductor by conducting load change, temperature rise and fall, and control precision experiments. The experimental study showed that the chiller had 2.1-3.9 kW of cooling capacity and 0.56-0.93 of EER. The control precisions were ${\pm}1^{\circ}C$ and ${\pm}0.6^{\circ}C$ when the setting temperatures were $0^{\circ}C$ and $30^{\circ}C$ respectively.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.2
• /
• pp.81-87
• /
• 1994

We used IR laser inteferometric technique for measuring the temperature of wafer during cryogenic ECR etching. Using this technique, the effect of RF bias power and microwave power on the wafer temperature during etching period is investigated. As the RF bias power and microwave power was increased, the temperature of the wafer considerably increased and we concluded that to prevent the increase of substrate temperature during etching period, an adequate wafer cooling is needed.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2012.10a
• /
• pp.657-658
• /
• 2012

• 제어로봇시스템학회:학술대회논문집
• /
• 2000.10a
• /
• pp.358-358
• /
• 2000

An iterative learning control technique based on a linear quadratic optimal criterion is proposed for temperature uniformity control of a silicon wafer in rapid thermal processing.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.24 no.5
• /
• pp.190-195
• /
• 2014

Because of the temperature gradient occurring during the growth of the ingot with directional solidification method, defects are generated and the residual stress is produced in the ingot. Changing the growth and cooling rate during the crystal growth process will be helpful for us to understand the defects and residual stress generation. The defects and residual stress can affect the properties of wafer. Generally, it was found that the size of grains and twin boundaries are smaller at the top area than at the bottom of the ingot regardless of growth and cooling condition. In addition to that, in the top area of silicon ingot, higher density of dislocation is observed to be present than in the bottom area of the silicon ingot. This observation implies that higher stress is imposed to the top area due to the faster cooling of silicon ingot after solidification process. In the ingot with slower growth rate, dislocation density was reduced and the TTV (Total Thickness Variation), saw mark, warp, and bow of wafer became lower. Therefore, optimum growth condition will help us to obtain high quality silicon ingot with low defect density and low residual stress.

• Journal of the Microelectronics and Packaging Society
• /
• v.27 no.3
• /
• pp.89-93
• /
• 2020

Complex warpage behavior of the electronic packages causes internal stress so many kinds of mechanical failure occur such as delamination or crack. Efforts to predict the warpage behavior accurately in order to prevent the decrease in yield have been approached from various aspects. For warpage prediction, silicon is generally treated as a homogeneous material, therefore it is described as showing no warpage behavior due to thermal loading. However, it was reported that warpage is actually caused by residual stress accumulated during grinding and polishing in order to make silicon wafer thinner, which make silicon wafer inhomogeneous through thickness direction. In this paper, warpage behavior of the single-side polished wafer at solder reflow temperature, the highest temperature in packaging processes, was measured using 3D digital image correlation (DIC) method. Mechanism was verified by measuring coefficient of thermal expansion (CTE) of both mirror-polished surface and rough surface.