• Journal of the Korean Institute of Telematics and Electronics
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• v.5 no.1
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• pp.13-25
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• 1968

A detailed analysis of the transistor wide-band feedback amplifiers using the hybrid-$\pi$ equivalent circuit has been made. It is considered both for the low freqnency and for the high frequency. The expressions of the gain, bandwidth. input impedance and output impedance have been presented. It is shown that a series feedback amplifier should be driven from the voltage source and should drive into the low resistance load, and a shunt feedback amplifier should be driven from the current source and should drive into the high resistance load. It is also shown that these stages can be coupled without use of the buffer stage or coupling transformer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1858-1863
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• 2000

본 논문에서는 SPD(Sampling Phase Detector)를 이용한 위상고정 방법의 무선 CATV용 위상 고정 유전체 공진 발진기(PLDRO)를 설계·제작하였다. 이 발진기는 하이브리드 형태인 12.875 GHz의 VCDRO(Voltage Controlled Dielectric Resonator Oscillator)와 완충 증폭기, 방향성 결합기, 주파수 체배기, 샘플링 위상 검출기, 루프 필터, 기준 주파수 발진기, VHF 증폭기로 구성되어 있다. 위상 고정 유전체 공진 발진기의 발진출력은 25.75 GHz에서 1.17 dBm, 기본주파수 억압 -27.83 dBc로 안정된 위상고정 상태를 나타내었다. 이때의 위상잡음은 -101.7 dBc/Hz @ 100KHz로 측정되었다.

• Journal of IKEEE
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• v.14 no.2
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• pp.51-57
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• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.268-272
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• 2001

In this thesis, PLVCO(Phase Locked Voltage Controlled Oscillator) using 24.42 GHz voltage controlled hair-pin resonator oscillator, Sequency divider, buffer amplifier, -10 dB directional coupler and phase detector is designed and fabricated for B-WLL. The PLVCO shows the oscillator output power of 16.5 dBm at 24.42 GHz, and phase noise of -76.3 dBc/Hz at 1001:Hz offset, -72.8dBc/Hz at 10 kHz offset from fundamental frequency.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2001.11a
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• pp.235-238
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• 2001

단일 단말기로부터 멀티 통신이 가능하게 됨에 따라 광대역 또는 듀얼대역에서 사용되는 RF 소자 개발이 중요시되고 있다. 그러므로 소형, 저 비용의 멀티대역 VCO(Voltage Controlled Oscillator)개발이 요구된다. 본 논문에서 GSM/DCN 대역에서 사용 가능한 듀얼밴드 VCO을 설계하였다. 하나의 발진부, 듀얼 공진부, 완충증폭기, 스위치회로로 구성되었으며, 위상 보정 기법을 이용하여 각 밴드에 대한 발진 조건을 만족시키므로 사용 부품의 수를 줄일 수 있어 저 비용, 소형화, 낮은 위상잡음(phase noise)을 얻을 수 있다. 설계된 듀얼 VCO는 GSM 대역에서 -110dBc/Hz(100kHz offset) 이하의 위상 잡음과 DCN 대역에서 -108dBc/Hz(100kHz offset)의 위상 특성을 보인다. 출력전력은 0$\pm$3dBm이며 소비전력 7mA로 만족할만한 성능을 보인다.

• Journal of Advanced Navigation Technology
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• v.3 no.1
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• pp.1-12
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• 1999

For the phase measurement of radar signal in the coherent-on-receiver system, the COHO(Coherent Oscillator) generates the signal which locks to the phase of the transmit pulse. In this paper, COHO unit is developed to generate 60 MHz phase-locked signal. ILO(Injection Locking Oscilator) locks to the sample of the transmit pulse. Gate circuit, ILO, buffer amplifier, and pulse generator are designed and implemented.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.6
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• pp.816-824
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• 1999

Design and performance of 18 GHz phase locked dielectric resonator oscillator(PLDRO) for Point-to-point radio link using analog phase locked loop is described which achieve high stability and low SSB phase noise. The module consists of an 18 GHz voltage controlled dielectric resonator oscillator(VCDRO), buffered amplifier, analog phase detector which are integrated to form a miniature hybrid circuit. In addition, containing a low phase noise VHF PLL has been designed to lock any other conventional N times frequency of crystal oscillator. The module achieves stable phase locked state, exhibits output power of 21 dBm at 18.00 GHz, -34 dBc harmonic suppression and -75 dBc/Hz phase noise at 10 kHz offset frequency from carrier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.586-591
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• 2000

In this paper, a PLHRO(Phase Locked Hair-pin Resonator Oscillator) for K-band is designed with the feedback property of PLL(Phase Locked Loop) using a new tuning mechanism. The proposed PLHRO generates the output power of -0.6 dBm at 24.42 GHz, and has the phase noise of -86.6 dBc/Hz at 100 KHz and -76.5 dBc/Hz at 10KHz offset from carrier frequency, and has suppression characteristics of -23 dBc and spurious noise of -65 dBc. Buffered 24.42 GHz PLHRO generates the output power of 5.6 dBm at 24.42 GHz and has the of a phase noise of -77.34 dBc/Hz at 100 KHz and -72 dBc/Hz at 100 KHz offset from carrier frequency.