• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.11
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• pp.1713-1719
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• 2022

As the noise canceler with a small processing delay increases the sampling frequency, a better-quality output can be obtained. For a single buffer, processing delay occurs because it is impossible to write new data while the processor is processing the data. When synthesizing with anti-noise and output signal, this processing delay creates additional buffering overhead to match the phase. In this paper, we propose an accelerator structure that minimizes processing delay and increases processing speed by alternately performing read and write operations using the Symmetric Even-Odd-buffer. In addition, we compare the structural differences between the two methods of noise cancellation (Fast Fourier Transform noise cancellation and adaptive Least Mean Square algorithm). As a result, using an Symmetric Even-Odd-buffer the processing delay was reduced by 29.2% compared to a single buffer. The proposed Symmetric Even-Odd-buffer structure has the advantage that it can be applied to various canceling algorithms.

• Journal of the Korea Society of Computer and Information
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• v.19 no.9
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• pp.125-139
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• 2014

In this paper, I propose a response modeling with a Semi-Supervised Support Vector Regression (SS-SVR) algorithm. In order to increase the accuracy and profit of response modeling, unlabeled data in the customer dataset are used with the labeled data during training. The proposed SS-SVR algorithm is designed to be a batch learning to reduce the training complexity. The label distributions of unlabeled data are estimated in order to consider the uncertainty of labeling. Then, multiple training data are generated from the unlabeled data and their estimated label distributions with oversampling to construct the training dataset with the labeled data. Finally, a data selection algorithm, Expected Margin based Pattern Selection (EMPS), is employed to reduce the training complexity. The experimental results conducted on a real-world marketing dataset showed that the proposed response modeling method trained efficiently, and improved the accuracy and the expected profit.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.109-116
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• 2007

Most harmonic synthesis methods using phase information employ a quadratic or cubic phase interpolation. The methods are computationally expensive to implement because every component sinewave must be synthesized on a per sample basis. In this paper, we propose a fast harmonic synthesis method for sinusoidal speech/audio coding based on the quadratic and cubic phase function to overcome the complexity problem. To derive the fast harmonic synthesis method, we define the over-sampling function and phase modulation function by constraining the parameter of phase function to be independent for harmonic index and derive the fast synthesis method using IFFT. Experimental results show that the proposed method significantly reduce the complexity of conventional cosine synthesis method while maintaining the performance.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.5
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• pp.331-337
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• 2023

In this paper, we propose a deep learning model to detect lumbar 3 (L3) CT images to determine the occurrence and degree of sarcopenia. In addition, we would like to propose an optimization technique that uses oversampling ratio and class weight as design parameters to address the problem of performance degradation due to data imbalance between L3 level and non-L3 level portions of CT data. In order to train and test the model, a total of 150 whole-body CT images of 104 prostate cancer patients and 46 bladder cancer patients who visited Gangneung Asan Medical Center were used. The deep learning model used ResNet50, and the design parameters of the optimization technique were selected as six types of model hyperparameters, data augmentation ratio, and class weight. It was confirmed that the proposed optimization-based L3 level extraction model reduced the median L3 error by about 1.0 slices compared to the control model (a model that optimized only 5 types of hyperparameters). Through the results of this study, accurate L3 slice detection was possible, and additionally, we were able to present the possibility of effectively solving the data imbalance problem through oversampling through data augmentation and class weight adjustment.

• Journal of KIISE:Software and Applications
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• v.33 no.2
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• pp.201-219
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• 2006

The key to developing software with the lowest cost and highest quality is to implement or fit the software development process into a given environment. Generally, applying commercial or standard software development processes on a specific project can cause too much overhead if there is no effort to customize the given generic processes. Even though the customizing activities are done before starting the project, these activities are thoroughly dependent on the process engineers who have abundant experience and knowledge with tailoring processes. Owing to this dependence on human knowledge, it has been very difficult to explain the rationale for the results of process tailoring and it takes a long time to get the customized process that is applicable. Hence, we suggest a process tailoring method which adopts the artificial neural network based teaming theory to reduce the time consumed by process tailoring. Furthermore, we suggest the feedback loop mechanism to get higher accuracy in the neural network designed for the process tailoring. It can be done by reusing the process tailoring data results and determining its appropriateness level as sample data to the neural network. We proved the effectiveness of our process tailoring method through case studies using real historical data, which yielded abundant process tailoring results as sample data.

• Journal of the Korea Computer Graphics Society
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• v.14 no.2
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• pp.19-25
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• 2008

We synthesize a texture with different structures at different scales. Our technique is based on deterministic parallel synthesis allowing real-time processing on a GPU. A new coordinate transformation operator is used to construct a synthesized coordinate map based on different exemplars at different scales. The runtime overhead is minimal because this operator can be precalculated as a small lookup table. Our technique is effective for upsampling texture-rich images, because the result preserves texture detail well. In addition, a user can design a texture by coloring a low-resolution control image. This design tool can also be used for the interactive synthesis of terrain in the style of a particular exemplar, using the familiar 'raise and lower' airbrush to specify elevation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.6-14
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• 2011

This paper presents the design of the battery sensor IC for instrumentation of current, voltage using delta-sigma ADC. The proposed circuit consists of programmable gain instrumentation amplifier (PGIA) and second-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a 0.25 ${\mu}m$ CMOS technology. Design circuit show that the modulator achieves 82 dB signal-to-noise ratio (SNR) over a 2 kHz signal bandwidth with an oversampling ratio (OSR) of 256 and differential nonlinearity (DNL) of ${\pm}$ 0.3 LSB, integral nonlinearity (INL) of ${\pm}$ 0.5 LSB. Power consumption is 4.5 mW.

• Journal of IKEEE
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• v.22 no.3
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• pp.786-792
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• 2018

A third-order sigma-delta modulator with the architecture of cascade of integrator feedback (CIFB) is proposed for an analog-digital converter used in low-power sensor interfaces. It consists of three switched-capacitor integrators using a gain-enhanced current-mirror-based amplifier, a single-bit comparator, and a non-overlapped clock generator. The proposed sigma-delta analog modulator with over-sampling ratio of 160 and maximum SNR of 90.45 dB is implemented using $0.11-{\mu}m$ CMOS process with 1.2-V supply voltage. The area and power consumption of the sigma-delta analog modulator are $0.145mm^2$ and $341{\mu}W$, respectively.

• Journal of IKEEE
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• v.18 no.2
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• pp.263-271
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• 2014

This paper presents design of the second-order sigma-delta modulator for converting voltage and temperature signals to digital ones in Battery Management IC (BMIC) for mobile applications. The second-order single-loop switched-capacitor sigma-delta modulator with 1-bit quantization in 0.13-um CMOS technology is proposed. The proposed modulator is designed using switched-opamp technique for saving power consumption. With an oversampling ratio of 256 and clock frequency of 256kHz, the modulator achieves a measured 83-dB dynamic range and a peak signal-to-(noise+distortion) ratio (SNDR) of 81.7dB. Power dissipation is about 0.66 mW at 3.3 V power supply and the occupied core area is $0.425mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.12
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• pp.1588-1594
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• 2020

In this paper, we discuss a data balancing method for learning a neural network that generates digital holograms using a deep neural network (DNN). Deep neural networks are based on deep learning (DL) technology and use a generative adversarial network (GAN) series. The fringe pattern, which is the basic unit of a hologram to be created through a deep neural network, has very different data types depending on the hologram plane and the position of the object. However, because the criteria for classifying the data are not clear, an imbalance in the training data may occur. The imbalance of learning data acts as a factor of instability in learning. Therefore, it presents a method for classifying and balancing data for which the classification criteria are not clear. And it shows that learning is stabilized through this.