• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.798-801
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• 2010

This paper describes an efficient architecture for LDPC(Low-Density Parity Check) decoder, which supports three block lengths (648, 1,296, 1,944) of IEEE 802.11n standard. To minimize hardware complexity, the min-sum algorithm and block-serial layered structure are adopted in DFU(Decoding Function Unit) which is a main functional block in LDPC decoder. The optimized H-ROM structure for multi block lengths reduces the ROM size by 42% as compared to the conventional method. Also, pipelined memory read/write scheme for inter-layer DFU operations is proposed for an optimized operation of LDPC decoder.

• Journal of Broadcast Engineering
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• v.17 no.4
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• pp.625-633
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• 2012

Extended Depth of Focus (EDF) algorithms for extracting three-dimensional (3D) information from a set of optical image slices are studied by many researches recently. Due to the limited depth of focus of the microscope, only a small portion of the image slices are in focus. Most of the EDF algorithms try to find the in-focus area to generate a single focused image and a 3D depth image. Inherent to most image processing algorithms, the EDF algorithms need parameters to be properly initialized to perform successfully. In this paper, we select three popular transform-based EDF algorithms which are each based on pyramid, wavelet transform, and complex wavelet transform, and study the performance of the algorithms according to the initialization of its parameters. The parameters we considered consist of the number of levels used in the transform, the selection of the lowest level image, the window size used in high frequency filter, the noise reduction method, etc. Through extended simulation, we find a good relationship between the initialization of the parameters and the properties of both the texture and 3D ground truth images. Typically, we find that a proper initialization of the parameters improve the algorithm performance 3dB ~ 19dB over a default initialization in recovering the 3D information.

• Journal of Broadcast Engineering
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• v.10 no.2
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• pp.238-246
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• 2005

This paper proposes an iterative high-resolution image interpolation algorithm using spatially adaptive constraints and regularization functional. The proposed algorithm adapts adaptive constraints according to the direction of..edges in an image, and can restore high-resolution image by optimizing regularization functional at each iteration, which is suitable for edge directional regularization. The proposed algorithm outperforms the conventional adaptive interpolation methods as well as non-adaptive ones, which not only can restore high frequency components, but also effectively reduce undesirable effects such as noise. Finally, in order to evaluate the performance of the proposed algorithm, various experiments are performed so that the proposed algorithm can provide good results in the sense of subjective and objective views.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2006.11a
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• pp.111-115
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• 2006

스케일러블 비디오 코딩(SVC, Scalable Video Coding)은 MPEG(Moving Picture Expert Group)과 VCEG (Video Coding Expert Group)의 JVT(Joint VIdeo Team)에 의해 현재 표준화 되고 있는 새로운 압축 표준 기술이며 시간, 공간 및 화질의 스케일러빌리티를 지원하기 위해 계층 구조를 가지고 있다. 특히 시간적 스케일러빌리티를 위해 계층적 B-픽처 구조를 채택하고 있다. 스케일러블 비디오 코딩의 기본 계층은 H.264|AVC와 호환적이므로, 모션 예측과 모드 결정과정에서 $16{\times}16,\;16{\times}8,\;8{\times}16,\;8{\times}8,\;8{\times}4,\;4{\times}8$ 그리고 $4{\times}4$와 같은 7개의 서로 다른 크기를 갖는 블록을 사용한다. 스케일러블 비디오 코딩에서 사용되고있는 계층적 B-픽처 구조는 키 픽처인 I와 P 픽처를 제외하고는 한 GOP (Group of Picture)내에서 모두 B-픽처를 사용하므로 H.264|AVC와 비교했을 때 연산량 증가와 함께 부호화 지연도 급격히 증가한다. B-픽처는 양방향 모션 벡터인 LIST0와 LIST1을 사용하고 양방향 모두에서 다중 참조 픽처를 사용하기 때문이다. 본 논문에서는 통계적 가선 검증을 이용하여 스케일러블 비디오 부호화에 적용 가능한 고속 프레임간 모드 결정 알고리듬 대해 소개한다. 제안된 방법은 $16{\times}16$ 매크로 블록과 $8{\times}8$ 서브 매크로 블록에 통계적 가설 감증 기법을 적용하여 실행되며, 현재 블록과 복원된 참조 블록간의 픽셀 값을 비교하여 RD(Rate Distortion) 최적화 기반 모드 결정을 빨리 완료함으로써 고속 프레임간 모드 결정을 가능하게 한다. 제안된 방법은 프레임 간 모드 결정을 고속화함으로써 스케일러블 비디오 부호화기의 연산량과 복잡도를 최대 57%감소시킨다. 그러나 연산량 감소에 따른 비트율의 증가나 화질의 열화는 최대 1.74% 비트율 증가 및 0.08dB PSNR 감소로 무시할 정도로 작다.

• Journal of Digital Contents Society
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• v.16 no.5
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• pp.805-813
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• 2015

Many researchers expect the compressive sensing and sparse recovery problem can overcome the limitation of conventional digital techniques. However, these new approaches require to solve the l1 norm optimization problems when it comes to signal reconstruction. In the signal reconstruction process, the transform computation by multiplication of a random matrix and a vector consumes considerable computing power. To address this issue, parallel processing is applied to the optimization problems. In particular, due to huge size of original signal, it is hard to store the random matrix directly in memory, which makes one need to design a procedural approach in handling the random matrix. This paper presents a new parallel algorithm to calculate random partial Haar wavelet transform based on Single Instruction Multiple Threads (SIMT) platform.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1617-1622
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• 2004

MPEG/Audio decoder for mobile multimedia systems requires low power consumption. Implementations of AV decoder using a single RISC processor often need high power consumption owing to cash-miss in case of insufficient cash memory. In this paper, we present a MPEG/Audio decoder for mobile handset applications and implement it on a RISC processor embedding a minimized DSP accelerator. Audio decoding algorithm is splined into two parts; computation intensive and control intensive parts. Those parts we, respectively, allocated to DSP and RISC core, which are designed to run in parallel to increase the processing efficiency. The proposed system implements MP3 and AAC decoders at l7MHz and 24MHz clocks, which are reductions of 48% and 40% of complexities in comparison with implementations on a single RISC processor. The proposed method is adequate for mobile multimedia applications with insufficient cash memory.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.5
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• pp.29-38
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• 1985

In this paper we have designed and implemented in real time a simple, efficient and flexible AOPCM cosec using a high speed digital processor, NEC 7720. For ADPCM system, we have used an instantaneous adaptive quantizer and a first-order fixed predictor. The software for NEC 7720 has been developed and it was found that the NEC 7720 was capable of performing the entire ADPCAt algorithm for 4 channels in real time as optimizing the program. Computer simulation has born made to investigate a computational accuracr of NEC 7720 and to de-termine necessary parameters for a ADPCM codec. Real telephone speech, RC-shaped Gaussian noise and 1004 Hz tone signal were used for simulation. In simulation, the parameters werc optimized from the computed SNR and the informal listening test. The developed software was tested in real time operation using a hardware emulator for NEC 7720. It took a maximum 23.25$\mu$s to encode one sample and 113.5$\mu$s, including all the necessary 1/0 operations, to encode 4 channels. In the case of decoding process, it took 24.75$\mu$s to decode one sample and 119.5$\mu$s to decode 4 channels.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.415-418
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems such as WiMAX and WLAN. The conventional DFU which is based on min-sum decoding algorithm needs conversions between two's complement values and sign-magnitude values, resulting in complex hardware. In this paper, a new design of DFU that is based on sign-magnitude arithmetic is proposed to achieve a simplified circuit and high-speed operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2465-2473
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11C
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• pp.1029-1039
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• 2009

In this paper, the existing disparity aquisition algorithms were analyzed, on the bases of which a disparity generation technique that is superior in accuracy to the generation time was proposed. Basically it uses a pixel-by-pixel motion estimation technique. It has a merit of possibility of a high-speed operation. But the motion estimation technique has a disadvantage of lower accuracy because it depends on the similarity of the matching window regardless of the distribution characteristics of the texture in an image. Therefore, an enhanced technique to increase the accuracy of the disparity is required. This paper introduced a variable-sized window matching technique for this requirement. By the proposed technique, high accuracies could be obtained at the homogeneous regions and the object edges. A hardware to generate disparity image was designed, which was optimized to the processing speed so that a high throughput is possible. The hardware was designed by Verilog-HDL and synthesized using Hynix $0.35{\mu}m$ CMOS cell library. The designed hardware was operated stably at 120MHz using Cadence NC-VerilogTM and could process 15 frames per second at this clock frequency.