• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1172-1179
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• 2022

This paper describes a design of point scalar multiplier for public-key cryptography based on binary Edwards curves (BEdC). For efficient implementation of point addition (PA) and point doubling (PD) on BEdC, projective coordinate was adopted for finite field arithmetic, and computational performance was improved because only one inversion was involved in point scalar multiplication (PSM). By applying optimizations to hardware design, the storage and arithmetic steps for finite field arithmetic in PA and PD were reduced by approximately 40%. We designed two types of point scalar multipliers for BEdC, Type-I uses one 257-b×257-b binary multiplier and Type-II uses eight 32-b×32-b binary multipliers. Type-II design uses 65% less LUTs compared to Type-I, but it was evaluated that it took about 3.5 times the PSM computation time when operating with 240 MHz. Therefore, the BEdC crypto core of Type-I is suitable for applications requiring high-performance, and Type-II structure is suitable for applications with limited resources.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.100-105
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• 2003

In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12C
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• pp.977-983
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• 2010

The output values of chaotic functions look highly unpredictable and random-like. These features are in accord with the requirements for secure cryptosystems. For this reason, many kinds of cryptosystems using chaotic functions have been proposed so far. However, most of those algorithms are not applicable for light cryptosystems because they need a high level of computing ability. In this paper, we propose a new light chaotic cryptosystems which are suitable for the systems with a low level of computing ability. From the simulations, we show the performance of proposed cryptosystems on computational complexity and security level.

• Journal of the Korea Society of Computer and Information
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• v.6 no.2
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• pp.20-26
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• 2001

The research into the conditions of the active rules is a very important element in the enhancing of the performance of the active database, and the processing time of the calculation generated from the conditions must be minimized in order to improve performance. In this paper, we propose the conditions processing system with the preprocessor which determines the delta tree structure and constructs the classification tree. Due to the characteristics of the active database through which the active rules can be comprehended beforehand. the preprocessor can be introduced. In this paper, the delta tree and classification tree which can effectively Process the join and selection operations instead of the delta relation is proposed. enhancing the condition evaluation performance.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.1009-1017
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• 2011

Fast generation of digital hologram is of importance for real-time holography broadcasting. In this paper, we propose such a method that parallelizes the Computer-Generated Holography (CGH) algorithm for digital hologram generation and make it faster using Multi Graphic Processing Unit (Multi-GPU) with help of the Compute Unified Device Architecture (CUDA) and the Open Multi-Processing (OpenMP). In addition, we propose optimization methods such as fixation variable, vectorization, and loop unrolling for making the CGH algorithm much faster. Experimental results show that our method is about 9,700 times faster than a CPU-based one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.3
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• pp.575-583
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• 2000

Pulse oximetry is a well established non-invasive optical technique for monitoring the $SpO_2$ during anaesthesia, recovery and intensive care. Pulse oximeters determine the oxygen saturation level of blood by measuring the light absorption of arterial blood. In the measurement of the hemoglobin oxygen saturation, conventional method has required the technique of filtering of remove the noise, and of complex signal processing algorithm. So much time have been required to signal processing. In this research, we separate AC signal and DC signal in the stage of signal detection. Therefore we simplify the calculation algorithm for $SpO_2$. The implemented system have the high performance such an accuracy and a processing time than the traditional method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.6
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• pp.1163-1168
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• 2001

The ranging systems measure range data in three-dimensional coordinate from target surface. These non-contact remote ranging systems is widely used in various automation applications, including military equipment, construction field, navigation, inspection, assembly, and robot vision. The active ranging systems using time of flight technique or light pattern illumination technique are complex and expensive, the passive systems based on stereo or focusing principle are time-consuming. The proposed algorithm, that is based on cross correlation of projection profile of vertical edge, provides advantages of fast and simple operation in the range acquisition. The results of experiment show the effectiveness of the proposed algorithm.

• Journal of KIISE:Databases
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• v.37 no.1
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• pp.33-43
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• 2010

In this paper, we propose a new location acquisition scheme based on RFID that reduces the computation cost of location acquisition and keeps the accuracy of the location. In addition, we propose an incremental location update policy to reduce the location update cost for moving objects. To show the superiority of our proposed scheme, we compare it with the existing researches. It is shown through various experiments that the proposed system reduces the computation cost of location estimation 500 times more than existing researches. Also, the proposed system significantly reduces the cost of location update using the RFID-based update policy.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.2
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• pp.327-338
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• 2018

On-line/off-line signature is a technique for performing heavy computations required for signature generation in the off-line stage and completing the final signature by a simple operation in the online stage. This is suitable for application environments that require immediate signing responses to multiple users. In this paper, we propose two new on-line/off-line signature schemes based on RSA problem. The first technique can generate a signature with a fixed base exponentiation when signing online, and the second technique can complete an online signature with a very simple calculation such as a hash operation. The security of both signatures is based on the RSA problem, which is proven to be tightly secure without security loss in the random oracle model.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.771-777
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• 2012

This paper proposes a binary arithmetic encoder of CABAC using a Common Operation Unit including the three modes. The binary arithmetic encoder performing arithmetic encoding and renormalizer can be simply implemented into a hardware architecture since the COU is used regardless of the modes. The proposed binary arithmetic encoder of CABAC includes Context RAM, Context Updater, Common Operation Unit and Bit-Gen. The architecture consists of 4-stage pipeline operating one symbol for each clock cycle. The area of proposed binary arithmetic encoder of CABAC is reduced up to 47%, the performance of proposed binary arithmetic encoder of CABAC is 19% higher than the previous architecture.