• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.576-582
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• 2011

In this paper, we proposed the improved Advanced Detail Enhancement algorithm that improve the blurring by the lossy compression with CODEC and reduce the ringing artifacts in restoration. The conventional algorithm needs much amount of the process by the use of RGB color space. To improve this, we only used the luminance value in YCbCr color space. We verified that the performance of the improved algorithm with Y color value, the luminance value, is equal to the conventional algorithm with RGB color value and that the operation time of the improved is shorter about 24% than the conventional through the measurement of the operation time with Kodak standard images.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1231-1238
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• 2005

This paper presents a new fast encoding algorithm for image vector quantization that incorporates the partial distances of multiple features with a multidimensional look-up table (LUT). Although the methods which were proposed earlier use the multiple features, they handles the multiple features step by step in terms of searching order and calculating process. On the other hand, the proposed algorithm utilizes these features simultaneously with the LUT. This paper completely describes how to build the LUT with considering the boundary effect for feasible memory cost and how to terminate the current search by utilizing partial distances of the LUT Simulation results confirm the effectiveness of the proposed algorithm. When the codebook size is 256, the computational complexity of the proposed algorithm can be reduced by up to the $70\%$ of the operations required by the recently proposed alternatives such as the ordered Hadamard transform partial distance search (OHTPDS), the modified $L_2-norm$ pyramid ($M-L_2NP$), etc. With feasible preprocessing time and memory cost, the proposed algorithm reduces the computational complexity to below the $2.2\%$ of those required for the exhaustive full search (EFS) algorithm while preserving the same encoding quality as that of the EFS algorithm.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.73-82
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• 2014

The LM algorithm is used in solving the least square problem in a non linear system, and is used in various fields. However, in cases the applied field's target functionis complicated and high-dimensional, it takes a lot of time solving the inner matrix and vector operations. In such cases, the LM algorithm is unsuitable in embedded environment and requires a hardware accelerator. In this paper, we implemented the LM algorithm in hardware. In the implementation, we used pipeline stages to divide the target function operation, and reduced the period of data input of the matrix and vector operations in order to accelerate the speed. To measure the performance of the implemented hardware, we applied the refining fundamental matrix(RFM), which is a part of 3D reconstruction application. As a result, the implemented system showed similar performance compared to software, and the execution speed increased in a product of 74.3.

• Journal of IKEEE
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• v.16 no.4
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• pp.349-355
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• 2012

Information technology improves convenience, safety, and performance of automobiles. Recently, a lot of algorithms are studied to provide safety and environment information for driving, and lane detection algorithm is one of them. In this paper, we propose a lane detection algorithm that reduces the amount of calculation by reducing region of interest (ROI) after preprocessing. The proposed algorithm reduces the area of ROI a lot by determining the candidate regions near lane boundaries as V-ROI so that the amount of calculation is reduced. In addition, the amount of calculation can be maintained almost the same regardless of the resolutions of the input images by compressing the images since the lane detection algorithm does not require high resolution. The proposed algorithm is implemented using C++ and OpenCV library and is verified to work at 30 fps for realtime operation.

• Journal of IKEEE
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• v.20 no.3
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• pp.209-219
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• 2016

SVM is a machine learning method used for image processing. It is well known for its high classification performance. We have to perform multiple MAC operations in order to use SVM for image classification. However, if the resolution of the target image or the number of classification cases increases, the execution time of SVM also increases, which makes it difficult to be performed in real-time applications. In this paper, we propose an hardware architecture which enables real-time applications using SVM classification. We used parallel architecture to simultaneously calculate MAC operations, and also designed the system for several feature extractors for compatibility. RBF kernel was used for hardware implemenation, and the exponent calculation formular included in the kernel was modified to enable fixed point modelling. Experimental results for the system, when implemented in Xilinx ZC-706 evaluation board, show that it can process 60.46 fps for $1360{\times}800$ resolution at 100MHz clock frequency.

• Journal of the Korea Society of Computer and Information
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• v.25 no.2
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• pp.1-10
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• 2020

In this paper, we propose an efficient disk buffer replacement policy which improves hit ratio and reduces writing operations of flash based storages. The flash based storage has many advantages, including a small form factor, non-volatility and high reliability, but there are problems caused by own limitations, like not-in-place update, short life cycle and asymmetric I/O latencies. To redeem these problems, this paper proposes the write weighted probability of reference(2WPR) policy. 2WPR policy predicts re-referencing probability and calculates localities of each page. Furthermore, by weighting write operations to every pages, 2WPR can reduce write operations to flash based storage. In addition, we can improve the performance with higher hit ratio and reduce the number of write operations and consequently shorten the latencies of each operation. The results show that our policy provides improvements of up to 10% for the hit ratio with the reduction of up to 5% for the flash writing operation compared with other policies.

• Journal of Korea Society of Industrial Information Systems
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• v.13 no.3
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• pp.110-116
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• 2008

In this paper, we proposed an improvement technique of image encryption using binary phase computer generated hologram(BPCGH) and multi exclusive-OR(XOR) operations. For the encryption process, a BPCGH that reconstructs the original image is designed, using an iterative algorithm, and the resulting hologram is regarded as the image to be encrypted. The BPCGH is encrypted through the exclusive-OR operation with the random generated phase key image. Then the encrypted image is divided into several slide images using XOR operations. So, the performance of encryption for the image is improved. For the decryption process, we cascade the encrypted slide images and phase key image and interfere with reference wave. Then decrypted hologram image is transformed into phase information. Finally, the original image is recovered by an inverse Fourier transformation of the phase information. If the slide images are changed, we can get various decrypted BPCGH images. In the proposed security system, without a random generated key image, the original image can not be recovered. And we recover another hologram pattern according to the slide images, so it can be used in the differentiated authorization system.

• Convergence Security Journal
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• v.17 no.2
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• pp.15-22
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• 2017

This paper presents new 8-bit implementation of AES. Most typical 8-bit AES designs are to reduce the circuit area by sacrificing its throughput. The presented AES architecture employs two separated S-box to perform round operation and key generation in parallel. From the simulation results of the proposed AES-128, the maximum critical path delay is 13.0ns. It can be operated in 77MHz and the throughput is 15.2 Mbps. Consequently, the throughput of the proposed AES has 1.54 times higher throughput than the other counterpart although the area increasement is limited in 1.17 times. The proposed AES design enables very low-area design without sacrificing its performance. Thereby, it can be suitable for the various IoT applications that need high speed communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.1046-1054
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• 2008

Since the high quality digital TV systems are broadly deployed in the market, the digital video contents will be edited and distributed in MPEG-2 MP@HL fonnat. Due to its impressive coding efficiency, the H.264/AVC codec has rapidly replaced the MPEG-4 SP codec for mobile digital video terminal with low quality. For the bro ad distribution of digitial video contents produced in MPEG-2 format, the MPEG-2 to H.264/AVC transcoding is highly necessary nowadays. In this paper, we propose a fast intra MB prediction mode decision method to reduce the computational complexity in the transcoding, which is the main bottleneck in the transcoders. The proposed method is based on the several relationships such as DCT coefficients and edge orientation, correlation between prediction directions in the $Intra16{\times}16$ and $Intra4{\times}4$ modes, correlation between edge-orientations of luminance an d chrominance components. The simulation results show that the proposed method can reduce the computational complexity upto 70% and 40%, compared with the cascaded transcoder and the well-known fast intraframe transc oder, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1491-1497
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• 2004

The psychoacoustic model in MPEG audio layer-III (MP3) encoder is optimized for the fixed-point processing. The optimization process consists of determining the data word length of arithmetic unit and the algorithm for transcendental functions that are often used in the psychoacoustic model. In order to determine the data word length, we defined a statistical model expressing the relation between the fixed-point operation errors of the psychoacoustic model and the probability of alteration of the allocated bits doe to these errors. Based on the simulations using this model, we chose a 24-bit data path and constructed a 24-bit fixed-point MP3 encoder. Sound quality tests using the constructed fixed-point encoder showed a mean degradation of -0.2 on ITU-R 5-point audio impairment scale.