• Journal of Digital Contents Society
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• v.17 no.1
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• pp.51-57
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• 2016

Distributed Computing attempts to harness a massive computing power using a great numbers of idle PCs resource distributed linked to the internet and processes a variety of applications parallel way such as bio, climate, cryptology, and astronomy. In this paper, we develop internet-distributed computing environment, so that we can analyze High Resolution Rainfall Prediction application in meteorological field. For analyze the rainfall forecast in Korea peninsula, we used QPM(Quantitative Precipitation Model) that is a mesoscale forecasting model. It needs to a lot of time to construct model which consisted of 27KM grid spacing, also the efficiency is degraded. On the other hand, based on this model it is easy to understand the distribution of rainfall calculated in accordance with the detailed topography of the area represented by a small terrain model reflecting the effects 3km radius of detail and terrain can improve the computational efficiency. The model is broken down into detailed area greater the required parallelism and increases the number of compute nodes that efficiency is increased linearly.. This model is distributed divided in two sub-grid distributed units of work to be done in the domain of $20{\times}20$ is networked computing resources.

• Journal of Digital Contents Society
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• v.15 no.6
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• pp.663-673
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• 2014

The WBAN technology means a short distance wireless network which provides each device interactive communication by connecting devices inside and outside of body. Standardization on the physical layer, data link layer, network layer and application layer is in progress by IEEE 802.15.6 TG BAN. Wireless body area network is usually configured in energy efficient using sensor and zigbee device due to the power limitation and the characteristics of human body. Wireless sensor network consist of sensor field and sink node. Sensor field are composed a lot of sensor node and sink node collect sensing data. Wireless sensor network has capacity of the self constitution by protocol where placed in large area without fixed position. In this paper, we proposed the efficient addressing scheme for improving the performance of routing algorithm by using ZigBee in WBAN environment. A distributed address allocation scheme used an existing algorithm that has wasted in address space. Therefore proposing x, y and z coordinate axes from divided address space of 16 bit to solve this problems. Each node was reduced not only bitwise but also multi hop using the coordinate axes while routing than Cskip algorithm. I compared the performance between the standard and the proposed mechanism through the numerical analysis. Simulation verified performance about decrease averaging multi hop count that compare proposing algorithm and another. The numerical analysis results show that proposed algorithm reduced the multi hop better than ZigBee distributed address assignment

• Journal of the Korea Society of Computer and Information
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• v.5 no.2
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• pp.30-36
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• 2000

The hidden node plays a role of the functional units that classifies the features of input pattern in the given question. Therefore, a neural network that consists of the number of a suitable optimum hidden node has be on the rise as a factor that has an important effect upon a result. However there is a problem that decides the number of hidden nodes based on back-propagation learning algorithm. If the number of hidden nodes is designated very small perfect learning is not done because the input pattern given cannot be classified enough. On the other hand, if designated a lot, overfitting occurs due to the unnecessary execution of operation and extravagance of memory point. So, the recognition rate is been law and the generality is fallen. Therefore, this paper suggests a method that decides the number of neural network node with feature information consisted of the parameter of learning algorithm. It excludes a node in the Pruning target, that has a maximum value among the feature value obtained and compares the average of the rest of hidden node feature value with the feature value of each hidden node, and then would like to improve the learning speed of neural network deciding the optimum structure of the multi-layer neural network as pruning the hidden node that has the feature value smaller than the average.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.25-33
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• 2006

We propose a method that automatically classifies the images into the object and non-object images. An object image is the image with object(s). An object in an image is defined as a set of regions that lie around center of the image and have significant color distribution against the other surround (or background) regions. We define four measures based on the characteristics of an object to classify the images. The center significance is calculated from the difference in color distribution between the center area and its surrounding region. Second measure is the variance of significantly correlated colors in the image plane. Significantly correlated colors are first defined as the colors of two adjacent pixels that appear more frequently around center of an image rather than at the background of the image. Third one is edge strength at the boundary of candidate for the object. By the way, it is computationally expensive to extract third value because central objects are extracted. So, we define fourth measure which is similar with third measure in characteristic. Fourth one can be calculated more fast but show less accuracy than third one. To classify the images we combine each measure by training the neural network and SYM. We compare classification accuracies of these two classifiers.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.97-104
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• 2016

Because of rapid growth of data size, the number of data storage has been increased. When using multiple data storages, a distribute file system is essential to insure the availability of data files. The power consumption is a major problem when using a distributed file system with many data storages. Previous works have aimed at reducing the energy consumption with efficient file block layout by changing some data servers into stand-by mode. The file block migration has not been seriously considered because migration causes large cost. But when we consider addition of a new data server or file, file block migration is needed. This paper formulates the minimization of data block migration as an ILP optimization problem and solves it using branch-and-bound method. Using this technique, we can maximize the number of stand-by data servers with the minimum number of file block movement. However, computation time of branch-and-bound method of an ILP optimization problem increases exponentially as the problem size grows. Therefore this paper also proposes a data block and data server grouping method to solve many small ILP problems.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.59-67
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• 2016

A novel instrumentation amplifier (IA) using fully-differential linear operational transconductance amplifier (FLOTA) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of a FLOTA, two resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into FLOTA converts into two same difference currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the FLOTA and realized the IA used commercial op-amp LF356. Simulation results show that the FLOTA has linearity error of 0.1% and offset current of 2.1uA at input dynamic range ${\pm}3.0V$. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the 60dB was 10MHz. The proposed IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 105mW at supply voltage of ${\pm}5V$.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.150-159
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• 2014

The latest video coding standard, HEVC can improve the coding efficiency significantly compared with the H.264/AVC. However the HEVC encoder requires much larger computational complexities. The longer 8-tap interpolation filter of the HEVC which is used in a non-integer motion estimation is one of the reasons and this paper aims to reduce the computational complexities. First of all, three shorter-tap interpolation filters for a motion estimation process are tested rather than the use of a standard interpolation filter. In addition, the fast searching strategies to reduce the number of comparisons for choosing the best non-integer motion vector are proposed. Finally, the interpolation process is selectively applied according to the searching strategy. By combining all of the techniques, the experimental results show that the encoding times can be reduced by 13.6%, 18.5% and 21.1% with the coding efficiency penalties of 0.7%, 1.5% and 2.5%, respectively. For the full-HD video sequences, the coding efficiency penalties are reduced to 0.4%, 1.1% and 1.6% at the same level of the encoding time savings, which shows the effectiveness of the proposed schemes for the high resolution video sequences.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.327-334
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• 2016

In this paper, we propose a hardware architecture of transform and quantization for high-perfornamce HEVC(High Efficiency VIdeo Coding) encoder. HEVC transform decides the transform mode by comparing RDCost to search for the best mode of them. But, RDCost is computed using the bit-rate and distortion which is computed by transform, quantization, de-quantization, and inverse transform. Due to the many calculations and encoding time, it is hard to process high resolution and high definition image in real-time. This paper proposes the method of transform mode decision by comparing sum of coefficient after transform only. We use BD-PSNR and BD-Bitrate which is performance indicator. Based on the experimental result, We confirmed that the decision of transform mode can process images with no significant change in the image quality. We reduced hardware area by assigning different values at the same output according to the transform mode and overlapping coefficient multiplied as much as possible. Also, we raise performance by implementing sequential pipeline operation. In view of the larger process that we used compared with the process of reference paper, Our design has reduced by half the hardware area and has increased performance 2.3 times.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.6
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• pp.460-469
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• 2015

This study's aim is for reducing big data transfer time of IoT healthcare devices by modulating digital bits into Manchester code including zero-voltage idle as information for secondary compressed binary cluster's compartment after two step compression of compressing binary data into primary and secondary binary compressed clusters for each binary clusters having compression benefit of 1 bit or 2 bits. Also this study proposed that as department information of compressed binary clusters, inserting idle signal into Manchester code will have benefit of reducing transfer time in case of compressing binary cluster into secondary compressed binary cluster by 2 bits, because in spite of cost of 1 clock idle, another 1 bit benefit can play a role of reducing 1 clock transfer time. Idle signal is also never consecutive because the signal is for compartment information between two adjacent secondary compressed binary cluster. Voltage transition on basic rule of Manchester code is remaining while inserting idle signal, so DC balance can be guaranteed. This study's simulation result said that even compressed binary data by another compression algorithms could be transferred faster by as much as about 12.6 percents if using this method.