• The Journal of the Korea Contents Association
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• v.9 no.10
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• pp.40-50
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• 2009

Incorrect deployment of RFID readers occurs reader-to-reader interferences in many applications using RFID technologies. Reader-to-reader interference occurs when a reader transmits a signal that interferes with the operation of another reader, thus preventing the second reader from communicating with tags in its interrogation zone. Interference detected by one reader and caused by another reader is referred to as a reader collision. In RFID systems, the reader collision problem is considered to be the bottleneck for the system throughput and reading efficiency. In this paper, we propose a novel RFID reader anti-collision algorithm based on evolutionary algorithm(EA). First, we analyze characteristics of RFID antennas and build database. Also, we propose EA encoding algorithm, fitness algorithm and genetic operators to deploy antennas efficiently. To show superiority of our proposed algorithm, we simulated our proposed algorithm. In the result, our proposed algorithm obtains 95.45% coverage rate and 10.29% interference rate after about 100 generations.

• Journal of KIISE:Databases
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• v.30 no.1
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• pp.80-94
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• 2003

In this paper. we propose an enhanced concurrency control algorithm that minimizes the query delay efficiently. The factors that delay search operations and deteriorate the concurrency of index structures are node splits and MBR updates in multi dimensional index structures. In our algorithm, to reduce the query delay by split operations, we optimize exclusive latching time on a split node. It holds exclusive latches not during whole split time but only during physical node split time that occupies small part of whole split time. Also to avoid the query delay by MBR updates we introduce partial lock coupling(PLC) technique. The PLC technique increases concurrency by using lock coupling only in case of MBR shrinking operations that are less frequent than MBR expansion operations. For performance evaluation, we implement the proposed algorithm and one of the existing link technique-based algorithms on MIDAS-III that is a storage system of a BADA-III DBMS. We show through various experiments that our proposed algorithm outperforms the existing algorithm In terms of throughput and response time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2405-2411
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• 2009

MMSE, ZF and ML are the decoding mechanisms for V-BLAST system, and ML shows the best performance decoding the original signal among them. However, it has a problem that the computation complexity is increased exponentially according to the number of transmit antennas and transmit degrees. In this paper, we propose a low complexity linear ML detection algorithm having low computation complexity, then analyze the system performance in BER and computation complexity comparing with other algorithms. In the simulation, the BER performance of the proposed algorithm is superior than ZF and MMSE detection algorithms, and similar to ML detection algorithm. However, its computation complexity was 50% less than ML algorithm. From the results, we confirm that the proposed algorithm is superior than other ML detection algorithms.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.97-105
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• 2015

This paper discusses the implementation of Bruun's FFT on a SIMD processor. FFT is an algorithm used in digital signal processing area and its effective processing is important in the enhancement of signal processing performance. Bruun's FFT algorithm is one of fast Fourier transform algorithms based on recursive factorization. Compared to popular Cooley-Tukey algorithm, it is advantageous in computations because most of its operations are based on real number multiplications instead of complex ones. However it shows more complicated data alignment patterns and requires a larger memory for storing coefficient data in its implementation on a SIMD processor. According to our experiment result, in the processing of the FFT with 1024 complex input data on a SIMD processor, The Bruun's algorithm shows approximately 1.2 times higher throughput but uses approximately 4 times more memory (20 Kbyte) than the Cooley-Tukey algorithm. Therefore, in the case with loose constraints on silicon area, the Bruun's algorithm is proper for the processing of FFT on a SIMD processor.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.11-19
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• 2014

In this paper, a low complexity parallel sphere decoder algorithm is proposed for high-order MIMO system. It reduces the computational complexity compared to the fixed-complexity sphere decoder (FSD) algorithm by static tree-pruning and dynamic tree-pruning using scalable node operators, and offers near-maximum likelihood decoding performance. Moreover, it also offers hardware-friendly node operation algorithm through fixing the variable computational complexity caused by the sequential nature of the conventional SD algorithm. A Monte Carlo simulation shows our proposed algorithm decreases the average number of expanded nodes by 55% with only 6.3% increase of the normalized decoding time compared to a full parallelized FSD algorithm for high-order MIMO communication system with 16 QAM modulation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.2
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• pp.241-251
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• 2015

In public-key cryptographic system based on finite field arithmetic, it is very important to challenge for implementing high speed operation. In this paper, we focused on 8-bit ATmega128 processor and concentrated on enhancing efficiency of reduction operation which uses irreducible polynomial $f(x)=x^{271}+x^{207}+x^{175}+x^{111}+1$ and $f(x)=x^{193}+x^{145}+x^{129}+x^{113}+1$. We propose optimized reduction algorithms which are designed to reduce repeated memory accesses by calculating final reduced values of Fast reduction. There are 53%, 55% improvement when proposed algorithm is implemented using assembly language, compare to previous Fast reduction algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2253-2260
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• 2012

In this paper, an efficient hardware architecture is proposed for inverse transform and inverse quantization of H.264/AVC decoder. The previous inverse transform and quantization architecture has a different AC and DC coefficients decoding order. In the proposed architecture, IQ is achieved after IT regardless of the DC or AC coefficients. A common operation unit is also proposed to reduce the computational complexity of inverse quantization. Since division operation is included in the previous architecture, it will generate errors if the processing order is changed. In order to solve the problem, the division operation is achieved after IT to prevent errors in the proposed architecture. The architecture is implemented with 3-stage pipeline and a parallel vertical and horizontal IDCT is also implemented to reduce the operation cycle. As a result of analyzing the proposed ITIQ architecture operation cycle for one macroblock, the proposed one has improved by 45% than the previous one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6A
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• pp.555-561
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• 2002

In this paper, a new designed circuit of highly parallel multiplier using standard basis over $GF(2^m)$ is presented. Prior to construct the multiplier circuit, we provide the Vector Code Generate Module(VCGM) that generate each vector codes for multiplication. Using these VCGMs, we can get all vector codes necessary for operation and modular sum up each independent corresponding basis, respectively. Following the equations in this paper, we can design generalized multiplier to m. For the proposed circuit in this parer, we show the example in $GF(2^4)$ using VCGMs. In this paper, we build a multiplier with VCGMs, AND blocks, and EX-OR blocks. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer then other circuit. We verify the proposed circuit by functional simulation and show its result. Finally, we compare the circuit composition with other works and show its result with a table.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.92-101
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• 2004

This paper proposes a algorithm to extract the variety region (object) from video for the real-time encoding of MPEG-4 based. The previous object segmentation methods cannot used the videophone or videoconference required by real-time processing. It is difficult to transfer a video to real-time because it increased complexity for the operation of each pixel on the spatial segmentation and temporal segmentation method proposed by MPEG-4 Working Group. But algorithm proposed for this thesis not operates a pixel unit but operates a macro block unit. Thus this enables real-time transfer. But this algorithm cannot extract several object for a image using proposed algorithm as previous algorithm. On system constructed by encoder and decoder. A proposed algorithm inserted for encoder as pre-process.

• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.861-872
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• 2011

Many fast block-matching algorithms (BMAs) in motion estimation field reduce computational complexity by screening the number of checking points. Although many fast BMAs reduce computations, sometimes they should endure matching errors in comparison with full-search algorithm (FSA). In this paper, a novel fast BMA for constrained one-bit transform (C1BT)-based motion estimation is proposed in order to decrease the calculations of the block distortion measure. Unlike the classical fast BMAs, the proposed algorithm shows a new approach to reduce computations. It utilizes the binomial distribution based on the characteristic of binary plane which is composed of only two elements: 0 and 1. Experimental results show that the proposed algorithm keeps its peak signal-to-noise ratio (PSNR) performance very close to the FSA-C1BT while the computation complexity is reduced considerably.