• Journal of IKEEE
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• v.24 no.3
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• pp.901-908
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• 2020

This paper describes a method for scalable hardware implementation of modular inversion. The proposed scalable architecture has a one-dimensional array of processing elements (PEs) that perform arithmetic operations in 32-bit word, and its performance and hardware size can be adjusted depending on the number of PEs used. The hardware operation of the scalable processor for modular inversion was verified by implementing it on Spartan-6 FPGA device. As a result of logic synthesis with a 180-nm CMOS standard cells, the operating frequency was estimated to be in the range of 167 to 131 MHz and the gate counts were in the range of 60,000 to 91,000 gate equivalents when the number of PEs was in the range of 1 to 10. When calculating 256-bit modular inverse, the average performance was 18.7 to 118.2 Mbps, depending on the number of PEs in the range of 1 to 10. Since our scalable architecture for computing modular inversion in GF(p) has the trade-off relationship between performance and hardware complexity depending on the number of PEs used, it can be used to efficiently implement modular inversion processor optimized for performance and hardware complexity required by applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1460-1468
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• 2000

The goal of this research is the real-time implementation of MPEG-1 Layer III audio decoder using the fixed-point digital signal processor of TMS320C6201 The main job for this work is twofold: one is to convert floating-point operation in the decoder into fixed-point operation while maintaining the high resolution, and the other is to optimize the program to make it run in real-time with memory size as small as possible. We, especially, devote much time to the descaling module in the decoder for conversion of floating-point operation into fixed-point operation with high accuracy. The inverse modified cosine transform(IMDCT) and synthesis polyphase filter bank modules are optimized in order to reduce the amount of computation and memory size. After the optimization process, in this paper, the implemented decoder uses about 26% of maximum computation capacity of TMS320C6201. The program memory, data ROM, data RAM used in the decoder are about 6.77kwords, 3.13 kwords and 9.94 kwords, respectively. Comparing the PCM output of fixed-point computation with that of floating-point computation, we achieve the signal-to-noise ratio of more than 60 dB. A real-time operation is demonstrated on the PC using the sound I/O and host communication functions in the EVM board.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.2
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• pp.201-211
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• 2012

This paper addresses a Full Disk Encryption hardware processor for SATA HDD in a single FPGA design, and shows its experimental result using an FPGA board. The proposed processor mainly consists of two blocks: the first block processes XTS-AES block cipher which is the IEEE P1619 standard of storage media encryption and the second block executes the interface between SATA Host (PC) and Device (HDD). To minimize the performance degradation, we designed the XTS-AES block with the 4-stage pipelined structure which can process a 128-bit block per 4 clock cycles and has 4.8Gbps (max) performance. Also, we implemented the proposed design with Xilinx ML507 FPGA board and our experiment showed 140MB/sec read/write speed in Windows XP 32-bit and a SATA II HDD. This performance is almost equivalent with the speed of the direct SATA connection without FDE devices, hence our proposed processor is very suitable for SATA HDD Full Disk Encryption environments.

• Communications of Mathematical Education
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• v.26 no.1
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• pp.85-108
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• 2012

The comprehensive implication in justification activity that includes the proof in the elementary school level where the logical and formative verification is hard to come has to be instructed. Therefore, this study has set the following issues. First, what is the mathematical justification type shown in the Number and Operations, and Geometry? Second, what are the errors shown by students in the justification process? In order to solve these research issues, the test was implemented on 62 third grade elementary school students in D City and analyzed the mathematical justification type. The research result could be summarized as follows. First, in solving the justification type test for the number and operations, students evenly used the empirical justification type and the analytical justification type. Second, in the geometry, the ratio of the empirical justification was shown to be higher than the analytical justification, and it had a difference from the number and operations that evenly disclosed the ratio of the empirical justification and the analytical justification. And third, as a result of analyzing the errors of students occurring during the justification process, it was shown to show in the order of the error of omitting the problem solving process, error of concept and principle, error in understanding the questions, and technical error. Therefore, it is prudent to provide substantial justification experiences to students. And, since it is difficult to correct the erroneous concept and mistaken principle once it is accepted as familiar content that it is required to find out the principle accepted in error or mistake and re-instruct to correct it.

• The KIPS Transactions:PartD
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• v.10D no.3
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• pp.359-366
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• 2003

Although the reuse of the cached data for scrolling the map reduces the amount of passed data between client and server, it needs the conversions of data coordinates, selective deletion of objects, cache compaction and object structuring step in the clients. The conversion is a time- intensive operation due to limited resources of mobile phones such as low computing power, small memory. Therefore, in order to control the map efficiently in the vector map service based mobile phones, it is necessary to study the methods which reuse cached objects for reducing wireless network bandwidth and overwhelming the limited resources of mobile phones as well. This paper proposes the methods of reusing pre-received spatial objects for map control in the mobile vector map service system based on client-server architecture. The experiments conducted on the Web GIS systems with real data show that the proposed method is appropriate to map services for mobile phone. We also analyze the advantages and drawbacks between the reuse of cached data and transmission of raw data respectively.

• Journal of Internet Computing and Services
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• v.13 no.3
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• pp.83-91
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• 2012

Recently, column-oriented storage has become a progressive model for high-speed database systems because of its superior I/O performance. In this paper, we analysis traditional raw-oriented storage model and then propose a new column-aware storage management model using flash memory drive and assist drive to improve the effective performance of the high-speed column-oriented database system. Our storage management scheme called column-aware polarization improves the performance of update operation by dividing and compressing table columns into active-columns or inactive-columns, and balancing congested update operations using a assist drive in high workload periods. The results obtained from experimental tests show that our scheme improves the update throughput of column-oriented storage by 19 percent, and the response time by up to 49 percent.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.1
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• pp.19-27
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• 2007

In this paper, we develope and implement a TFT-LCD cell defects detection algorithm using morphology. To detect the bright line or dark line defects and the bright pixel or dark pixel defects of the TFT-LCD cells, we determine the shape of the morphology operators considering the shape characteristics of the TFT-LCD sub pixels. Using dilation, erosion, and the subtraction operators, we extract gray level defects information. Then, we apply the optimal threshold method which shows the best results in terms of several criteria. Finally, we determine the defects using labelling method. From various experiments using TFT-LCD panels, the proposed algorithm shows superior results.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.88-95
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• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.

• Journal of Elementary Mathematics Education in Korea
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• v.13 no.1
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• pp.17-30
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• 2009

This paper is about the basic skills of four operations in numbers and operations areas from step 1 to step 3 in elementary mathematics. Here are the results of the evaluation. First, addition and subtraction take the largest time. The average difficulty rate in operations area is 91.2%. Most students understand the contents of textbook well. Specifically, students easily understand the step 1. However, subtraction has lower difficulty rate than addition. Also, three mixed computation, calculation in horizontal, and rounding(rounding down) are difficult areas for students. The contents of step 2 are fully understood. However, lots of mistakes are found in the process of rounding(rounding down), and sentence problems are thought as difficult. Second, the multiplication is first starting in the step 2-Ga. The unit 'Multiplication 99' takes 13 hours, the longest. The difficulty rate in this unit is 89.4%, students understand well. However, students are influenced by addition and subtraction errors in the process of multiplication, and have difficulty in changing the sentence problem to multiplication expression. Third, the division, which starts in step 3-Ga, has 89.9% of difficulty rate. Students well understand. Result of this paper: most of students understand well four operations, but accurate concept, the relationship between multiplication and division, specific instructions in teaching principles of division calculation and sentence problems are in need. Setting the amount of the contents and difficulty rate in understanding are depends on every school's situation, so suggesting universal standard is really hard. However, studying more objects broadly and specific study will be helpful to suggest proper contents and effective teaching.

• Landscaping Tree
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• s.109
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• pp.9-13
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• 2009

황산벌 전투. 계백장군과 5천 결사대의 항전지. 백제와 후백제의 마지막 역사를 간직하고 있는 이곳 충남 아산시 연산면 청동리에 자리한 우리 조경수협회 본회 이사이며 충남조경수유통센터의 조합장을 맡고 있는 이상권 사장의 그린농원을 찾았다.