• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.89-93
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• 2002

This paper describes an ALU core which is suitable for 32-bit DSP This ALU operates in 32-bit data and occupies the third stage, execution, among 5 stage pipeline structure. The supplied functions of the ALU are arithmetic operations, logical operations, shifting, and so on. For the implementation of this ALU core, each functional block is described by HDL. And the functional verification of the ALU core is performed through HDL simulation. This ALU is designed to use the 32-bit DSP.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.4
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• pp.175-183
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• 1985

Dataflow computers exhibit a high degree of parallelism which can not be obtained easily with the conventional von-Neumann architecture. Since many instructions are ready for execution simultaneously, concurrency can be easily achieved by the multiple processors modified the dataflow machine. This paper describes a FFT Butterfly algorithm for dataflow computation and evaluates the performance by the speed up factor of that algorithm through the simulation approach by the time-accelation method.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2008.02a
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• pp.81-84
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• 2008

김재겸은 2005년 한국 멀티미디어 학회 논문지에 새로운 이차원 셀룰라 오토마타 설계 방법을 소개하고 이 설계 방법으로 구성된 이차원 셀룰라 오토마타를 이용한 해쉬함수를 제안하였다. 본 논문에서는 이 해쉬함수에 대한 첫 번째 분석 결과를 소개한다. 이 해쉬함수는 8 라운드로 구성되고 한 라운드는 두 개의 비선형 연산 부분을 포함하고 있으며, 메시지는 두 비선형 연산 부분에 모두 사용된다. 메시지 차분이 비선형 연산 부분을 거친 뒤 사라질 확률은 $2^{-14}$이다. 따라서 1 라운드 후 약 $2^{-28}$의 확률로 이 해쉬함수의 충돌쌍을 찾을 수 있다. 본 논문의 분석 결과를 통하여 이 해쉬함수는 매우 취약함을 알 수 있다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.6
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• pp.38-43
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• 1981

In this paper an actively compensatedfinite gain amplifie. (FGA) with positive gain using 4 operational amplifiers and resistors is propo sod, and an application is considered in an active RC filter. By cancelling the effect of the GB's up to the third-order term of s on the transfer function, the proposed FGA has the extended frequency range over that of the FGA using 3 operational amplifiers. When this FGA is applied to an active RC filter with Pole frequncy of 100kHz, the magnitude error of the frequency characteristics of the filter is less than 2%.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.288-294
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• 2000

In this paper, an efficient detail extraction technique for a progressive coding scheme is proposed. The existing technique using the top-hat transformation yields an efficient extraction scheme for isolated and visually important details, but yields an inefficient results containing significant redundancy extracting the contour information. The proposed technique using the strong edge feature extraction property of the morphological Laplacian in this paper can reduce the redundancy, and thus provides lower bit-rate. Experimental results show that the proposed technique is more efficient than the existing one, and promise the applicability of the morphological Laplacian operator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.9
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• pp.863-871
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• 2004

In this paper, we propose a subspace channel estimation technique for DS/CDMA DMB down link system, which can obtain reduction in numerical complexity by using of matched filtering outputs. The complexity reduction is considerable when the channel length is small and the system is moderately loaded. Previously proposed subspace-based blind channel estimation algorithm suffer from high numerical complexity for systems with large spreading gains. Although the proposed algerian suffers a slight performance loss, it becomes negligible for large observation length. Performance is evaluated through simulations and the derivation of the analytical MSE.

• Proceedings of the Korea Information Processing Society Conference
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• 2016.10a
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• pp.12-15
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• 2016

데이터베이스 시스템의 트랜잭션 로깅이나 파일 시스템의 저널링에서 데이터 저장시 입출력 동기화(Synchronous I/O)는 올바른 프로르램 동작에 필수적이다. 하지만 입출력 동기화로 인한 프로그램의 지연 혹은 기다림은 응용 프로그램 성능의 저하를 가져온다. 본 논문에서는 차세대 저장장치인 비휘발성 메모리를 사용하여 지속성을 보장하며 쓰기 연산의 응답성을 개선하는 사용자 수준의 스토리지 모듈을 제안하고 기존의 동기화된 쓰기 연산과 성능을 비교하였다. 특히 멀티코어 환경에서 동시에 들어오는 여러 입출력 쓰기 연산 요청에 대하여 효율적으로 처리하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3A
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• pp.231-237
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• 2010

Multi-input multi-output (MIMO) systems are used to improve the transmission rate in proportion to the number of antennas. However, their computational complexity is very high for the detection in the receiver. The sphere decoding (SD) is a detection algorithm with reduced complexity. In this paper, an improved Schnorr-Euchner SD (SE SD) is proposed based on the minimum mean square error (MMSE) and the Euclidean distance criteria without additional complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10A
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• pp.976-981
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• 2006

In this paper, we describe a hybrid ZF-SD method. The method is based on dimensionality reduction via predecoding and cancellation of those symbols that can be quickly and reliably detected by a linear decoder. The proposed method shows BER performance similar to SD but with much lower computational complexity than SD.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4C
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• pp.388-397
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• 2002

We designed a SIMD-DSP/FPU that can efficiently improve multimedia processing performance when integrated into high-performance embedded microprocessors. We proposed partitioned architectures and new schemes for several functional units to reduce chip area. Sharing functional units reduces the area of FPU significantly. The proposed architecture is modeled in HDL and synthesized with a 0.35$\mu\textrm{m}$ standard cell library. The chip area is estimated to be about 100,000 equivalent gates. The designed unit can run at higher than 50MHz clock frequency of CPU core under the worst-case operating conditions.