• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.6
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• pp.2713-2719
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• 2012

According to increasing of various location-based services, distributed data stream processing techniques have been widely studied to provide high scalability and availability. In previous researches, in order to balance the load of distributed nodes, the geographic characteristics of spatial data stream are not considered. For this reason, distributed operations for adjacent spatial regions increases the overall system load. We propose a operation allocation scheme considering the characteristics of spatial operations to effectively processing spatial data stream in distributed computing environments. The proposed method presents the efficient share maximizing approach that preferentially distributes spatial operations sharing the common query regions to the same node in order to separate the adjacent spatial operations on overlapped regions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7C
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• pp.946-953
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• 2004

Fast search and conventional boolean matching motion estimation algorithms reduce computational complexity and data processing time but this algorithms have disadvantages that is difficult of implementation of hardware because of high control overhead and that is less performance than Full search Algorithm(FA). This paper present new all binary block matching algorithm, called Bit Converted All Binary Block Matching(BC-ABBM). Proposed algorithm have performance closed to the FA by boolean only block matching that may be very efficiently implemented in hardware for low bit rate video communication. Simulation results show that the PSNR of the proposed algorithm is about 0.04dB loss than FA but is about 0.6 ∼ 1.4dB gain than fast search algorithm and conventional boolean matching algorithm.

• Journal of the Korea Society of Computer and Information
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• v.19 no.8
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• pp.107-117
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• 2014

This paper proposed the method of removing baseline drift by eliminating local maxima such as P, R, T-wave signal region and local minima Q, S-wave signal region. We applied morphology-pair operations improved from morphology operation to the ECG signal. To eliminate overshoot in the result of morphology-pair operation, we apply median value operation to the result of morphology-pair operation. We use MIT/BIH database to estimate the proposed algorithm. Experiment result show that proposed algorithm removing baseline drift effectively without orignal ECG signal distortion.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.56-62
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• 2003

In this paper, we designed a adder and a multiplier using current mode T-gate on $GF(2^2)$. The T-gate is consisted of current mirror and pass transistor, the designed 4-valued T-gate used adder and multiplier on $GF(2^2)$. We designed its under 1.5um CMOS standard technology. The unit current of the circuits is 15㎂, and power supply is 3.3V VDD. The proposed current mode CMOS operator have a advantage of module by T-gate`s arrangement, and so we easily implement multi-valued operator.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.9
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• pp.1055-1063
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• 1999

공개키 암호화 시스템에서 주된 연산은 512비트 이상의 큰 수에 의한 모듈러 지수 연산으로 표현되며, 이 연산은 내부적으로 모듈러 곱셈을 반복적으로 수행함으로써 계산된다. 본 논문에서는 Montgomery 알고리즘을 분석하여 right-to-left 방식의 모듈러 지수 연산에서 공통으로 계산 가능한 부분을 이용하여 모듈러 제곱과 모듈러 곱셈을 동시에 수행하는 선형 시스톨릭 어레이를 설계한다. 설계된 시스톨릭 어레이는 VLSI 칩과 같은 하드웨어로 구현함으로써 IC 카드나 smart 카드에 이용될 수 있다.Abstract The main operation of the public-key cryptographic system is represented the modular exponentiation containing 512 or more bits and computed by performing the repetitive modular multiplications. In this paper, we analyze Montgomery algorithm and design the linear systolic array for performing modular multiplication and modular squaring simultaneously using the computable part in common in right-to-left modular exponentiation. The systolic array presented in this paper could be designed on VLSI hardware and used in IC and smart card.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.9A
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• pp.2365-2371
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• 1998

Discrete cosine transform (DCT) has wide applications in speech and image coding. In this paper, we propose a novel fast dCT scheme with the property of reduced multiplication stages and the smaller number of additions and multiplications. This exploits the symmetry property of the DCT kernel to decompose the N-point dCT to N/2 point, and can be generally applied recursively to $2^{m}$-point. The proposed algorithm has a structure that most of multiplications tend to be performed at final stage, and this reduces propagation of truncation error which could occur in the fixed-point computation. Also the minimization of the multiplication stages further decreases the error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.324-330
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• 2004

In this paper, we propose the TCM(Trellis coded modulation) decoding scheme that reduces the number of operations in branch metric with STBC(space time block codes) channel information and present the implementation results. The proposed TCM decoding scheme needs only 1 signal point in each TCM subset. Using bias point scheme, It detects the minimum distance symbol. The proposed TCM decoding scheme can reduce the branch metric calculations. In case of 16QAM 8 subset, the reduction ratio is about 50％ and for 64QAM 8 subset, about 80％ reduction can be obtained. The results of logic synthesis for the TCM and STBC decoder with the proposed scheme are 57.6K gate count.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.5
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• pp.317-322
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• 2014

Data security and integrity is a critical issue in data transmission over wired/wireless links. A large amount of data is encrypted before transmission, by block cipher using mode of operation. RBF mode is a block cipher mode of operation which uses random characteristics. In this paper, we analyze the safety against known plaintext attack and chosen plaintext attack of RBF mode compared to the traditional modes. According to the analysis, RBF mode is known to be secure while the traditional modes are not secure against them.

• Journal of Korea Game Society
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• v.13 no.6
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• pp.43-52
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• 2013

Path finder is one of the very important algorithm of artificial intelligence and is a process generally used in many game fields. Path finder requires many calculation, so it exerts enormous influences on performances. To solve this, many researches on the ways to reduce the amount of calculate operations have been made, and the typical example is A* algorithm but it has unnecessary computing process, reducing efficiency. In this paper, to reduce the amount of calculate operations such as node search with costly arithmetic operations, we proposes the weight based pre-processing A* algorithm. The simulation was materialized to measure the efficiency of the weight based pre-process A* algorithm, and the results of the experiments showed that the weight based method was approximately 1~2 times more efficient than the general methods.

• Journal of Digital Contents Society
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• v.18 no.3
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• pp.613-619
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• 2017

This paper presents a CUDA (Compute Unified Device Architecture) code to achieve correct GPU parallel segmented prefix operation results with less than 32 segment length for large data arrays. Mark Harris and Michael Garland had published CUDA code to address the tasks. This paper shows that their code does not generate correct results when the local segment length is less than 32, discusses the cause of the problem, and presents a CUDA code that generates correct results. The segmented parallel prefix operation presented in this paper can be applied as a building block to various large parallel processing algorithms including the k-nearest neighbor search problems.