• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.1-9
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• 2004

The important arithmetic operations over finite fields include exponentiation, division, and inversion. An exponentiation operation can be implemented using a series of squaring and multiplication operations using a binary method, while division and inversion can be performed by the iterative application of an AB$^2$ operation. Hence, it is important to develop a fast algorithm and efficient hardware for this operations. In this paper presents new bit-serial architectures for the simultaneous computation of multiplication and squaring operations, and the computation of an $AB^2$ operation over $GF(2^m)$ generated by an irreducible AOP of degree m. The proposed architectures offer a significant improvement in reducing the hardware complexity compared with previous architectures, and can also be used as a kernel circuit for exponentiation, division, and inversion architectures. Furthermore, since the Proposed architectures include regularity and modularity, they can be easily designed on VLSI hardware and used in IC cards.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.8
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• pp.758-762
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• 2008

Embedded systems usually utilize Flash Memories with very nice characteristics of non-volatility, low access time, low power and so on. For the multimedia database systems, R-tree is an indexing tree with nice characteristics for multimedia access. MR-tree, which is an upgraded version of R-tree, has shown better performance in searching, inserting and deleting operations than R-tree. Flash memory has sectors and blocks as a unit of read, write and delete operations. Especially, the delete is done on a unit of 512 byte blocks with very large operation time and it is also known that read and write operations on a unit of block matches caching nature of MT-tree. Our research optimizes MR-tree operations in a unit of Flash memory blocks. Such an adjusting leads in better indexing performance in database accesses. With MR-tree on a 512B block units we achieved fast search time of database indexing with low height of MR-tree as well as faster update time of database indexing with the best fit of flash memory blocks. Thus MR-tree with optimized operations shows good characteristics to be a database index schemes on any systems with flash memory.

• Journal of The Korean Association of Information Education
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• v.17 no.1
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• pp.9-21
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• 2013

The purpose of this paper is to develop and implement a mobile application system to improve arithmetical operations for low achievers. The proposed system has the following characteristics. First, the system provides individual study for low achievers based on their different study levels. Second, instant feedback can be provided to students for maintaining study motivation. Third, the system enables students to study arithmetical operations in persistent and repetitive manner. This is due to that, in the literature, arithmetical operation capacity can be increased by persistent and repetitive practices. The proposed system is applied to mathematics low achievers and the following results are obtained. First, interests and intrinsic motivation are increased through use of the proposed system. Second, arithmetical operation speed is increased. Also, accuracy of arithmetical operation is improved. Thus, it is concluded that arithmetical operation capacity of low achievers is improved using the proposed system.

• Journal of the Korea Society of Computer and Information
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• v.15 no.2
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• pp.9-18
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• 2010

High performance is required with small size and low power in the mobile embedded system. A CORDIC algorithm can compute transcendental functions effectively with only small adders and shifters and is suitable one for the mobile embedded system. However CORDIC unit has performance degradation according due to iterative inter-rotations. Adder design is an important design unit to be optimized for a high performance and low power CORDIC unit. It is necessary to explore the design space of a CORDIC unit considering trade-offs of an adder unit while satisfying delay, area and power constraints. In this paper, we suggest a CORDIC architecture employing a heterogeneous adder and an optimization methodology for producing better optimal tradeoff points of CORDIC designs.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.124-129
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• 2013

This paper proposes a high-performance vector inner product calculation circuit for real-time object recognition based on SVM algorithm. SVM algorithm shows a higher detection rate than other object recognition algorithms. However, it requires a huge amount of computational efforts. Since vector inner product calculation is one of the major operations of SVM algorithm, it is important to implement a high-performance vector inner product calculation circuit for real-time object recognition capability. The proposed circuit adopts the pipeline architecture with six stages to increase the operating speed and makes it possible to recognize objects in real time based on SVM. The proposed circuit was described in Verilog HDL at RTL. For silicon verification, an MPW chip was fabricated using TSMC 180nm standard cell library. The operation of the implemented MPW chip was verified on the test board with test application software developed for the chip verification.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.4
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• pp.83-89
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• 2006

In H/W implementation for the finite field, the use of normal basis has several advantages, especially, the optimal normal basis is the most efficient to H/W implementation in GF($2^m$). In this paper, we propose a new, simpler, parallel multiplier over GF($2^m$) having a type II optimal normal basis, which performs multiplication over GF($2^m$) in the extension field GF($2^{2m}$). The time and area complexity of the proposed multiplier is same as the best of known type II optimal normal basis parallel multiplier.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1142-1147
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• 2022

The edges of image should be detected first so that the objects in the image can be identified. An hardware-implemented edge detection algorithm outperforms its software version. Sobel operation is the most suitable algorithm for an hardware implementation of edge detection. And lots of works have been done to perform Sobel operations efficiently on FPGA-based hardware. This work proposes how to implement fast edge detection circuit on FPGA, which is based on the conventional circuit for edge detection using Sobel operator. The newly proposed circuit is suitable for processing images when the images are stored in memory devices and outperforms the conventional one with little additional FPGA resources. Both the conventional circuit and the proposed circuit were implemented on an FPGA. And the result showed that the proposed circuit almost doubles the performance in processing images and needs little additional FPGA resources.

• Journal of the Korea Society of Computer and Information
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• v.13 no.2
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• pp.193-201
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• 2008

Using Network Coding in P2P systems yields great benefits, e.g., reduced download delay. The core notion of Network Coding is to allow encoding and decoding at intermediate nodes, which are prohibited in the traditional networking. However, improper implementation of Network Coding may reduce the overall performance of P2P systems. Network Coding cannot work with general arithmetic operations, since its arithmetic is over a Finite Field and the use of an efficient Finite Field arithmetic algorithm is the key to the performance of Network Coding. Also there are other important performance parameters in Network Coding such as Field size. In this paper we study how those factors influence the performance of Network Coding based systems. A set of experiments shows that overall performance of Network Coding can vary 2-5 times by those factors and we argue that when developing a network system using Network Coding those performance parameters must be carefully chosen.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.3
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• pp.7-12
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• 2016

DRAM is commonly used as a smartphone memory medium, but extending its capacity is challenging due to DRAM's large battery consumption and density limit. Meanwhile, smartphone applications such as social network services need increasingly large memory, resulting in long latency due to additional storage accesses. To alleviate this situation, we adopt emerging nonvolatile memory (NVRAM) as smartphone's buffer cache and propose an efficient management scheme. The proposed scheme stores all dirty data in NVRAM, thereby reducing the number of storage accesses. Moreover, it separately exploits read and write histories of data accesses, leading to more efficient management of volatile and nonvolatile buffer caches, respectively. Trace-driven simulations show that the proposed scheme improves I/O performances significantly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.874-882
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• 2004

MPEG Audio compression algorithm is the international standard for the digital compression of high quality audio using mechanism of the perceptual coding based on psychoacoustic masking. It is necessary to discuss the constraints on designing of common filter banks for MPEG-2 BC and MPEG-2 AAC decoder system, which is not Down yet, mapping audio signals from the time domain into the frequency domain. In this paper, we present an architecture of common synthesis filter whcih can be used for MPEG-2 BC and MPEG-2 AAC decoder using recursive structure. The proposed algorithm is based on recursive architecture that effectively performs common compulsion.