• KIPE Magazine
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• v.9 no.2
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• pp.26-30
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• 2004

전력전자 분야에서 사용되는 전동기 제어 시스템 또는 UPS, 능동필터 등 반도체 전력회로 제어에 다양한 신호처리와 고속연산이 가능하도록 하드웨어적으로 부동소숫점을 연산하거나 MAC 연산 기능 등이 있어 계산 속도가 빠르다는 장점 때문에 TMS320C3X등의 DSP가 많이 사용되어 왔다. 그런데 DSP는 입/출력 기능이 상당히 떨어지므로 외부에 A/D 변환기, EPLD 또는 FPGA 등의 외부소자 들이 많이 필요하여 회로가 상당히 복잡하다는 문제가 있었다. 이에 비하여 마이크로제어기는 입/출력 기능이 우수하나 연산속도가 상당히 떨어진다는 단점이 있다.(중략)

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.1-7
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• 1999

We present VLSI architecture for a high performance 2-D DCT processor which is used compressing system of real time image processing or HDTV using fast computational algorithm of the Optimized Integer Cosine Transform(OICT). The coefficients of the OICT are integer, so the OICT performs only the integer operations for both forward and inverse transform. Therefore the proposed architecture could be greatly enhanced in improving the speed, reduced the hardware cost considerably by replacing the multiplication operations with shift and addition operations compared with DCT which performs floating-point operations.

• The KIPS Transactions:PartA
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• v.16A no.5
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• pp.319-326
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• 2009

Since string operations were applied to computational biology area, various data structures and algorithms for computing efficient string operations have been studied. The longest common substring problem is an operation to find the longest matching substring in more than two strings, and maximal repeat of string problem is an operation to find substrings repeated more than once in the given string. These operations are importantly used in the string processing area such as pattern matching and likelihood measurement. In this paper, we present algorithms to compute the longest common substring of two strings and to find the maximal repeat of string using three-dimensional $n{\times}n{\times}n$ processors on RMESH(Reconfigurable MESH). Our algorithms have O(1) time complexity.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.11a
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• pp.218-221
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• 2014

기존의 지역기반 스테레오 정합 방법은 정합에 사용하는 정합창 크기에 따라 다양한 결과를 갖게 된다. 특히 사용하는 정합창의 크기가 커질수록 영상의 잡음에 강인하지만 객체의 경계부분이 모호해지는 단점을 갖고 있다. 본 논문은 고정된 크기의 정합창을 사용하는 지역기반 스테레오 정합 방법과 다른 방법을 제안한다. 제안한 방법은 영상의 경계를 검출하는 알고리즘을 이용하여 경계부분에는 작은 크기의 정합창을 사용한 변이값을 적용하고 경계가 없는 부분은 큰 크기의 정합창을 사용하여 얻은 변이값을 적용하도록 하였다. 경계를 검출하는 과정에서 본 논문은 AND 연산을 사용하여 최대한 객체의 테두리만을 나타내는 경계값을 구하도록 하였다. 또한 두 가지 크기의 정합창을 이용함으로써 발생하는 복잡도 증가를 감소시키기 위해 기존의 SAD 연산 알고리즘을 수정하여 복잡도를 감소시켰다. 본 논문에서 사용한 정합창의 크기는 $5{\times}5$와 $15{\times}15$이며 실험결과 제안한 방법은 $15{\times}15$ 정합창을 사용한 결과와 비교하여 변이지도에서 객체의 경계부분은 더 잘 살리면서 수행시간을 줄여 효율적인 정합결과를 얻어냈다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.06a
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• pp.96-99
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• 2018

최근 초고화질 영상뿐만 아니라 360 비디오 콘텐츠의 보급이 확산되고 있다. 이미 대중적으로 보급된 스마트폰을 통해 누구나 쉽게 이 360 비디오 콘텐츠를 접할 수 있는데, 스마트폰의 성능은 제한적일 수 밖에 없다. 따라서 본 논문은 모바일 VR 에서 360 비디오 병렬처리를 수행할 때 보다 적합한 최적화 방법 2 가지를 소개한다. 이를 위해 전력 소모를 줄이는 장점으로 인해 모바일 디바이스에 많이 사용되는 비대칭 멀티코어의 특징을 활용한다. 두 방법 모두 공통적으로 각 코어의 성능비와 할당되는 작업량을 비례하게 하여 디코딩 작업의 시간을 줄이는 방법들이다. 첫 번째 방법은 영상을 타일로 분할할 때 각 코어의 성능비와 비례하게 분할하는 방법이다. 해당 기법을 적용하기 위해서, 비디오 크기별 연산 복잡도 분석 모델을 활용하여 사용한다. 제안하는 기법을 사용한 실험 결과, 평균적으로 약 25%의 디코딩 시간 개선을 보였다. 두 번째 방법은 타일로 분할된 영상의 각 복잡도 정도를 PU 의 양으로 추정하여, 각 코어의 성능비와 비례하게 코어에 할당하는 방법이다. 해당 기법을 사용하기 위해서, PU 의 양과 연산 복잡도 정도의 상관관계를 회귀분석하여 이를 이용한다. 제안하는 기법을 사용한 실험 결과, 약 9~16%의 디코딩 시간 개선을 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.397-400
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• 2016

In this paper, we propose an efficient algorithm for computing architecture for high-performance Inter Prediction SAD HEVC encoder. HEVC Motion Estimation (ME) of the Inter Prediction is a process for searching for the currently high prediction block PU and the correlation in the interpolated reference picture in order to remove temporal redundancy. ME algorithm uses full search(FS) or fast search algorithm. Full search technique has the guaranteed optimal results but has many disadvantages which include high calculation and operational time due to the motion prediction with respect to all candidate blocks in a given search area. Therefore, this paper proposes a new algorithm which reduces the computational complexity by reusing the SAD operation in full search to reduce the amount of calculation and computational time of the Inter Prediction. The proposed algorithm is applied to an HEVC standard software HM16.12. There was an improved operational time of 61% compared to the traditional full search algorithm, BDBitrate was decreased by 11.81% and BDPSNR increased by about 0.5%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.66-72
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• 2009

This paper proposes an efficient binary arithmetic encoder for CABAC which is used one of the entropy coding methods for H.264/AVC. The present binary arithmetic encoding algorithm requires huge complexity of operation and data dependency of each step, which is difficult to be operated in fast. Therefore, renormalization exploits 2-stage pipeline architecture for efficient process of operation, which reduces huge complexity of operation and data dependency. Context model updater is implemented by using a simple expression instead of transIdxMPS table and merging transIdxLPS and rangeTabLPS tables, which decreases hardware size. Arithmetic calculator consists of regular mode, bypass mode and termination mode for appearance probability of binary value. It can operate in maximum speed. The proposed binary arithmetic encoder has 7282 gate counts in 0.18um standard cell library. And input symbol per cycle is about 1.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.3C
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• pp.175-182
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• 2011

This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a high throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a modified mixed-radix multi-path delay commutator structure and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the number of complex multipliers at the second stage from 88 to 40. The proposed FFT/IFFT processor has been designed and implemented with the 90nm CMOS technology. The proposed eight-parallel FFT/IFFT processor can provide a throughput rate of up to 27.5Gsample/s at 430MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.940-948
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• 2008

This paper presents a low-power, low-complexity design and implementation results of a high speed multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor is composed of the physical layer convergence procedure (PLCP) processor and physical medium dependent (PMD) processor, which have been optimized to have low-power and reduced-complexity architecture. It was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. As a result, the proposed TX-PLCP processor reduced the power consumption by as much as 81% over the bit-level operation architecture. Also, the proposed MIMO symbol detector reduced the hardware complexity by 18% over the conventional SQRD-based architecture with division circuits and square root operations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.798-809
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• 2013

In this paper, we propose robust relay and destination filter design methods for the multi-user peer-to-peer amplify-and-forward relaying systems while taking imperfect channel knowledge into consideration. Specifically, the relay and destination filter sets are developed to minimize the sum mean-squared-error (MSE). We first present a robust joint optimum relay and destination filter calculation method with an iterative algorithm. Motivated by the need to reduce computational complexity of the iterative scheme, we then formulate a simplified sum MSE minimization problem using the relay filter decomposability, which lead to two robust sub-optimum non-iterative design methods. Finally, we propose robust modified destination filter design methods which require only local channel state information between relay node and a specific destination node. The analysis and simulation results verify that, compared with the optimum iterative method, the proposed non-iterative schemes suffer a marginal loss in performance while enjoying significantly improved implementation efficiencies. Also it is confirmed that the proposed robust filter design methods provide desired robustness in the presence of channel uncertainty.