• Journal of KIISE
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• v.43 no.8
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• pp.933-945
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• 2016

Sharing data by multiple users on the public storage, e.g., the cloud, is considered to be efficient because the cloud provides on-demand computing service at anytime and anywhere. Secure data sharing is achieved by fine-grained access control. Existing symmetric and public key encryption schemes are not suitable for secure data sharing because they support 1-to-1 relationship between a ciphertext and a secret key. Attribute based encryption supports fine-grained access control, however it incurs linearly increasing ciphertexts as the number of attributes increases. Additionally, the decryption process has high computational cost so that it is not applicable in case of resource-constrained environments. In this study, we propose an efficient attribute-based secure data sharing scheme with outsourceable decryption. The proposed scheme guarantees constant-size ciphertexts irrespective of the number of attributes. In case of static attributes, the computation cost to the user is reduced by delegating approximately 95.3% of decryption operations to the more powerful storage systems, whereas 72.3% of decryption operations are outsourced in terms of dynamic attributes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.85-94
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• 2004

In this paper, a register allocation techlique that translates memory accesses to register accesses Is presented to enhance embedded software performance. In the proposed method, a source code is profiled to generate a memory trace. From the profiling results, target functions with high dynamic call counts are selected, and the proposed register allocation technique is applied only to the target functions to save the compilation time. The memory trace of the target functions is searched for the memory accesses that result in cycle count reduction when replaced by register accesses, and they are translated to register accesses by modifying the intermediate code and allocating Promotion registers. The experiments where the performance is measured in terms of the cycle count on MediaBench and DSPstone benchmark programs show that the proposed method increases the performance by 14% and 18% on the average for ARM and MCORE, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.123-130
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• 2016

In this paper, a high-performance arithmetic unit which can efficiently accelerate a number of algorithms for multimedia application was designed. The 3-stage pipelined arithmetic unit can execute 38 operations for complex and fixed-point data by using efficient configuration for four 16-bit by 16-bit multipliers, new sign extension method for carry-save data, and correction constant scheme to eliminate sign-extension in compression operation of multiple partial multiplication results. The arithmetic unit has about 300-MHz operating frequency and about 37,000 gates on 45nm CMOS technology and its estimated performance is 300 MCOPS(Million Complex Operations Per Second). Because the arithmetic unit has high processing rate and supports a number of operations dedicated to various applications, it can be efficiently applicable to multimedia processors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3A
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• pp.254-259
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• 2010

In this paper, we propose a low-complexity carrier frequency offset (CFO) estimation algorithm for OFDM based wireless LAN, IEEE 802.11a. The complexity of the arctangent operation to calculate the argument of auto-correlation for CFO estimation is reduced by a novel range pointer method. The proposed algorithm estimates fine CFO value first and then based on the fine CFO value, simple criteria is used for the boundary decision of integer CFO estimation. The simulation results show that the performance of the proposed algorithm is slightly better than the conventional method while the computational complexity is reduced by 50%. Furthermore, the proposed method can be easily implemented for the low complex next generation MIMO-OFDM based WLAN systems.

• The Journal of the Acoustical Society of Korea
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• v.27 no.3
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• pp.149-153
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• 2008

General underwater target detection methods adopt short-time FFT for estimate target doppler. This paper proposes the efficient target detection method, instead of conventional FFT, using approximate FFT for distributed sensor network target detection, which requires lighter computations. In the proposed method, we decrease computational rate of FFT by the quantization of received signal. For validation of the proposed method, experiment result which is applied to FFT based active sonar detector and real oceanic data is presented.

• Journal of Korea Spatial Information System Society
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• v.7 no.3 s.15
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• pp.55-65
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• 2005

This paper presents a bulk insertion technique for efficiently inserting data items. Traditional moving object database focused on efficient query processing that happens mainly after index building. Traditional index structures rarely considered disk I/O overhead for index rebuilding by inserting data items. This paper, to solve this problem, describes a new bulk insertion technique which efficiently induces the current positions of moving objects and reduces update cost greatly. This technique uses buffering technique for bulk insertion in spatial index structures such as R-tree. To analyze split or merge node, we add a secondary index for information management on leaf node of primary index. And operations are classified to reduce unnecessary insertion and deletion. This technique decides processing order of moving objects, which minimize split and merge cost as a result of update operations. Experimental results show that this technique reduces insertion cost as compared with existing insertion techniques.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.7C
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• pp.616-626
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• 2007

In spatially multiplexed MIMO systems that enable high data rate transmission over wireless communication channels, the spatial demultiplexing at the receiver is a challenging task, and various demultiplexing methods have been developed recently by many researchers. Among the previous methods, maximum likelihood detection with QR decomposition and M-algorithm (QRM-MM)), and sphere decoding (SD) schemes have been reported to achieve a (near) maximum likelihood (ML) performance. In this paper, we propose a novel signal detection method that achieves a near ML performance in a computationally efficient manner. The proposed method is demonstrated via a set of computer simulations that the proposed method achieves a near ML performance while requiring a complexity that is comparable to that of the conventional MMSE-OSIC. We also show that the log likelihood ratio (LLR) values for all bits are obtained without additional calculation but as byproduct in the proposed detection method, while in the previous QRM-MLD, SD, additional computation is necessary after the hard decision for LLR calculation.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10b
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• pp.60-62
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• 1998

무선 통신 기술이 발달함에 따라 이동 컴퓨팅 환경의 새로운 속성 및 조건들을 고려할 수 있는 새로운 알고리즘이 필요하게 되었다. 이 논문에서는 이동 컴퓨팅 환경에서 읽기 전용 트랜잭션의 직렬화가능한(serializable) 수행을 위한 스케쥴링 기법을 제안한다. 제안하는 기법에서는 이동 컴퓨터가 지역 캐쉬를 이용하여 읽기 연산을 수행하며, 서버와 특별한 제어 정보의 교환 없이 완료 혹은 철회되도록 한다. 이러한 연산의 수행을 위하여 충돌 연산의 순서를 데이터의 의미를 고려하여 재순서화 한다. 그리고 이동 컴퓨터는 서버의 주기적인 브로드캐스팅 정보를 이용하여 캐쉬 데이터의 유용성 검사를 수행한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2022.06a
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• pp.175-178
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• 2022

본 논문은 고차 계층 변조, 즉 계층 64QAM의 연판정 비트 검출을 위한 단순화된 연산 방법을 다룬다. 이는 기존 계층 변조의 연판정 비트, 즉 LLR(Log-Likelihood Ratio)값의 근사를 통해 불필요한 연산을 줄여 이에 필요한 지연시간을 줄일 수 있다. 또한 제안된 기법은 기존의 연판정 비트 검출 기법과 매우 유사한 비트 오류율(BER: Bit Error Rate) 성능을 유지하기 때문에 연판정 비트를 활용하는 방송 및 통신 시스템에 폭넓게 적용될 수 있을 것으로 기대한다.

• The Journal of the Korea Contents Association
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• v.13 no.3
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• pp.9-21
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• 2013

Due to increased computing power and flexibility of GPU, recent GPUs execute general purpose parallel applications as well as graphics applications. Programmers can use GPGPU by using the APIs from GPU vendors. Unfortunately, computational resources of GPU are not fully utilized when executing general purpose applications because of frequent branch instructions. To handle the branch problem, several warp formations have been proposed. Intuitively, we expect that the warp formations providing higher computational resource utilization show higher performance. Contrary to our expectations, according to simulation results, the performance of the warp formation providing better utilization is lower than that of the warp formation providing worse utilization. This is because warp formation providing high utilization causes serious memory bottleneck due to increased memory request. Therefore, warp formation providing high computation utilization cannot guarantee high performance without proper hardware resources. For this reason, we will analyze the correlation between hardware configuration and warp formation. Our simulation results present the guideline to solve the underutilization problem due to branch instructions when designing recent GPU.