• KOREAN POULTRY JOURNAL
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• v.51 no.10
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• pp.108-109
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• 2019

• KOREAN POULTRY JOURNAL
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• v.54 no.11
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• pp.134-134
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• 2022

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.4
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• pp.727-736
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• 2009

In this paper, the $arccos(cos^{-1})$ arithmetic unit for mobile graphics accelerator is designed. The mobile vector graphics applications need tight area, execution time, power dissipation, and accuracy constraints compared to desktop PC applications. The designed processor adopts 2nd-order polynomial approximation scheme based on IEEE floating point data format to satisfy speed and accuracy conditions and reduces area via hardware sharing structure. The arccosine processor consists of 15,280 gates and its estimated operating frequency is about 125Mhz at operating condition of $0.35{\mu}m$ CMOS technology. Because the processor can execute arccosine function within 7 clock cycles, it has about 17 MOPS(million arccos operations per second) execution rate and can be applicable to mobile OpenVG processor. And because of its flexible architecture, it can be applicable to the various transcendental functions such as exponential, trigonometric and logarithmic functions via replacement of ROM and minor hardware modification.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.292-295
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• 2003

블루투스 전송 기술은 2.4㎓ 의 ISM(Industrial Scientific Medicine)밴드에서 주파수 호핑 방식을 사용한다. 주파수 호핑율은 연결 상태에서 초당 1600회, 조회 또는 호출 상태에서 초당 3200회의 호핑을 한다. Hop 채널 선택은 블루투스 표준안에서 제시한 5개의 호핑 시퀸스 중 하나를 선택하고 호핑 주파수에 따라 이를 매핑 함으로써 이루어진다. 본 논문에서는 6개의 상태에 따라 다르게 실행되는 채널 계산을 효율적으로 제어하고 필요한 연산모듈의 수를 줄이기 위해 9비트 프로세서를 이용해 Hop 선택 모듈을 설계하고 구현한다. 설계된 모듈은 레지스터 파일, 마이크로프로그램 제어장치, 가산, 치환(permutation), Modulo 계산을 위한 3개의 연산장치로 구성된다. Hop 채널 계산 중 가장 클럭 소요가 큰 Modulo 연산은 SRT나눗셈 알고리즘을 사용하여 음수 값 계산 및 연산 속도 향상을 꾀하였다. 제시된 Hop 선택 모듈은 하드웨어 묘사언어인 VHDL로 설계하고 시뮬레이션 및 테스트는 Xilinx FPGA를 이용해 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.30-36
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• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. Although many word oriented memories as well as embedded memories in system-on-chip (SOC) consists of multiple local memory blocks with a global spare architecture, most of previous studies on built-in redundancy analysis (BIRA) algorithms have focused on single memory block with a local spare architecture. In this paper, a new BIRA algorithm for multiple blocks with a global spare architecture is proposed. The proposed BIRA is basd on CRESTA which is able to achieve optimal repair rate with almost zero analysis time. In the proposed BIRA, all repair solutions for local memory blocks are analyzed by local analyzers which belong to each local memory block and then compared sequentially and judged whether each solution can meet the limitation of the global spare architecture or not. Experimental results show that the proposed BIRA achieves much faster analysis speed compared to previous BIRAs with an optimal repair rate.

• Journal of KIISE
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• v.43 no.5
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• pp.541-552
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• 2016

This paper introduces the new notions of conjunctive and complement choices in process algebra, which reduce both process and system complexities significantly for distributed mobile real-time system during specification and analysis phases. The complement choice implies that two processes make cohesive choices for their synchronous partners at their own choice operations. The conjunctive choice implies choice dependency among consecutive choice operations in a process. The conjunctive choice reduces process complexity exponentially by the degree of the consecutive choice operations. The complement choice also reduces system complexity exponentially by the degree of the synchronous choice operations. Consequently, the reduction method makes the specification and analysis of the systems much easier since the complexity is reduced significantly. This notion is implemented in a process algebra, called ${\delta}$-Calculus. The efficiency and effectiveness are demonstrated with an example in a tool for the algebra, called SAVE, which is developed on ADOxx platform.

• Journal of KIISE
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• v.44 no.9
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• pp.871-877
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• 2017

A vast amount of research has been carried out for executing compute-intensive applications on resource-constrained mobile devices. Computation offloading is a method in which heavy computations are dynamically migrated from a mobile device to a server, exploiting the powerful hardware of the server to perform complex computations. An important issue for offloading is the complexity of reconciling the execution state of applications between the server and the client. To address this issue, snapshot-based offloading has recently been proposed, which utilizes the snapshot of a web app as the portable description of the execution state. However, for web applications using the HTML5 canvas, snapshot-based offloading does not function correctly, because the snapshot cannot capture the state of the canvas. In this paper, we propose a code generation technique to save the canvas state as part of a snapshot, so that the snapshot-based offloading can be applied to web applications using the canvas.

• Journal of KIISE:Databases
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• v.30 no.5
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• pp.540-551
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• 2003

Recently, several works have been proposed for updating XML documents［l-3] stored in databases. These researches defined update operations and resolved some semantic problems. Because the update operations are usually validated after execution, several conflicts nay occur. For solving these conflicts, XML database systems must be able to validate an update operation immediately according to DTD before the update operation is executed. Furthermore, in many studies for updating, they just validate whole XML documents and can't validate parts of them. If updates are very frequent, validating whole XML documents will cause performance degradation. In this paper, we propose solutions for these two problems. We extract and store DTD information. Then, when an XML document stored in the database is updated, we verifies whether the update is valid or not by using the information. Consequently, XML database systems can always maintain valid XML documents. The validity of update operations is checked immediately before the actual update operation is applied to the database and the validation is performed on only updated parts of an XML document in the database.

• Journal of Internet Computing and Services
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• v.14 no.1
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• pp.15-22
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• 2013

WAVE(Wireless Access for Vehicular Environment) is new concepts and Vehicles communications technology using for ITS(Intelligent Transportation Systems) service by IEEE standard 802.11p. Also it increases the efficiency and safety of the traffic on the road. However, the efficiency of Scrambler bit computational algorithms of OFDM modulation in WAVE systems will fall as it is not able to process in parallel in terms of hardware and software. This paper proposes an algorithm to configure 64-bits matrix table in scambler bit computation as well as an algorithm to compute 64-bits matrix table and input data in parallel. The proposed algorithm on this thesis is executed using 64-bits matrix table. In the result, the processing speed for 1 and 1000 times is improved about 40.08% ~ 40.27% and processing rate per sec is performed more than 468.35 compared to bit operation scramble. And processing speed for 1 and 1000 times is improved about 7.53% ~ 7.84% and processing rate per sec is performed more than 91.44 compared to 32-bits operation scramble. Therefore, if the 64 bit-CPU is used for 64-bits executable scramble algorithm, it is improved more than 40% compare to 32-bits scrambler.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.117-123
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• 2014

This paper proposes the constructing method of effective multiplier using basis transformation. Th proposed multiplier is composed of the standard-dual basis transformation circuit module to change one input into dual basis the operation module to generate from bm to bm+k by the m degree irreducible polynomial, and the polynomial multiplicative module to consist of $m^2$ AND and m(m-1) EX-OR gates. Also, the dual-standard basis transformation circuit module to change the output part to be shown as a dual basis into standard basis is composed. The operation modules to need in each operational part are defined.