• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.87-95
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• 1996

A new design scheme for the fuzzy pattern matching classifier (FPMC) is proposed. in conventional design of FPMC, there are no exact information about the membership function of which shape and number critically affect the performance of classifier. So far, a trial and error or heuristic method is used to find membership functions for the input patterns. But each of them have limits in its application to the various types of pattern recognition problem. In this paper, a new method to find the appropriate shape and number of membership functions for the input patterns which minimize classification error is proposed using genetic algorithms(GAs). Genetic algorithms belong to a class of stochastic algorithms based on biological models of evolution. They have been applied to many function optimization problems and shown to find optimal or near optimal solutions. In this paper, GAs are used to find the appropriate shape and number of membership functions based on fitness function which is inversely proportional to classification error. The strings in GAs determine the membership functions and recognition results using these membership functions affect reproduction of next generation in GAs. The proposed design scheme is applied to the several patterns such as tire tread patterns and handwritten alphabetic characters. Experimental results show the usefulness of the proposed scheme.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.29-39
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• 2015

This paper describes a design and implementation of fuzzy-based algorithm for hand-shake state detection and error compensation in the mobile optical image stabilization(OIS) motion detector. Since the gyro sensor output of the OIS motion detector includes inherent error signals, accurate error correction is required for prompt hand-shake error compensation and stable hand-shake state detection. In this research with a little computation overhead of fuzzy-based algorithm, the hand-shake error compensation could be improved by quickly reducing the angle and phase error for the hand-shake frequencies. Further, stability of the OIS system could be enhanced by the hand-shake states of {Halt, Little vibrate, Big vibrate, Pan/Tilt}, classified by subdividing the hand-shake angle. The performance and stability of the proposed algorithm in OIS motion detector is quantitatively and qualitatively evaluated with the emulated hand-shaking of ${\pm}0.5^{\circ}$, ${\pm}0.8^{\circ}$ vibration and 2~12Hz frequency. In experiments, the average error compensation gain of 3.71dB is achieved with respect to the conventional BACF/DCF algorithm; and the four hand-shake states are detected in a stable manner.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.127-132
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• 2011

In this paper, we propose a novel method of adult image classification by combining skin color regions and edges in an input image. The proposed method consists of four steps. In the first step, initial skin color regions are detected by logical AND operation of all skin color regions detected by the existing methods of skin color detection. In the second step, a skin color probability map is created by modeling the distribution of skin color in the initial regions. Then, a binary image is generated by using threshold value from the skin color probability map. In the third step, after using the binary image and edge information, we detect final skin color regions using a region growing method. In the final step, adult image classification is performed by support vector machine(SVM). To this end, a feature vector is extracted by combining the final skin color regions and neighboring edges of them. As experimental results, the proposed method improves performance of the adult image classification by 9.6%, compared to the existing method.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.4
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• pp.89-96
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• 2012

A 3D map provides useful information for intelligent services. Traditional 3D maps, however, consist of a raw image data and are not suitable for real-time applications. In this paper, we propose the Block-based 3D map, that represents three dimensional spaces in a collection of square blocks. The Block_based 3D map has two major variables: an object ratio and a block size. The object ratio is defined as the proportion of object pixels to space pixels in a block and determines the type of the block. The block size is defined as the number of pixels of the side of a block and determines the size of the block. Experiments show the advantage of the Block-based 3D map in reducing noise, and in saving the amount of processing data. With the block size of $40{\times}40$ and the object ratio of 30% to 50% we can get the most matched Block-based 3D map for the $320{\times}240$ depthmap. The Block-based 3D map provides useful information, that can produce a variety of new services with high added value in intelligent environments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.72-81
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• 2011

In this paper, we proposed and designed a novel floating point converter which supports single and double precisions of IEEE754 standard. The proposed convertor supports conversions between floating point number single/double precision and signed fixed point number(32bits/64bits) as well as conversions between signed integer(32bits/64bits) and floating point number single/double precision and conversions between floating point number single and double precisions. We defined a new internal format to convert various input types into one type so that overflow checking could be conducted easily according to range of output types. The internal format is similar to the extended format of floating point double precision defined in IEEE754 2008 standard. This standard specifies that minimum exponent bit-width of the extended format of floating point double precision is 15bits, but 11bits are enough to implement the proposed converting unit. Also, we optimized rounding stage of the convertor unit so that we could make it possible to operate rounding and represent correct negative numbers using an incrementer instead an adder. We designed single cycle data path and 5 cycles data path. After describing the HDL model for two data paths of the convertor, we synthesized them with TSMC 180nm technology library using Synopsys design compiler. Cell area of synthesis result occupies 12,886 gates(2 input NAND gate), and maximum operating frequency is 411MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.43-54
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• 2007

This paper presents design and verification of a face detection hardware for real time application. Face detection algorithm detects rough face position based on already acquired feature parameter data. The hardware is composed of five main modules: Integral Image Calculator, Feature Coordinate Calculator, Feature Difference Calculator, Cascade Calculator, and Window Detection. It also includes on-chip Integral Image memory and Feature Parameter memory. The face detection hardware was verified by using S3C2440A CPU of Samsung Electronics, Virtex4LX100 FPGA of Xilinx, and a CCD Camera module. Our design uses 3,251 LUTs of Xilinx FPGA and takes about 1.96${\sim}$0.13 sec for face detection depending on sliding-window step size, when synthesized for Virtex4LX100 FPGA. When synthesized on Magnachip 0.25um ASIC library, it uses about 410,000 gates (Combinational area about 345,000 gates, Noncombinational area about 65,000 gates) and takes less than 0.5 sec for face realtime detection. This size and performance shows that it is adequate to use for embedded system applications. It has been fabricated as a real chip as a part of XF1201 chip and proven to work.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Journal of KIISE:Software and Applications
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• v.36 no.7
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• pp.548-559
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• 2009

The cascade face detector learned by Adaboost algorithm, which was proposed by Viola and Jones, is state of the art face detector due to its great speed and accuracy. In spite of its great performance, it still suffers from false alarms, and more computation is required to reduce them. In this paper, we want to reduce false alarms with less computation using facial color. Using facial color information, proposed face detection model scans sub-window efficiently and adapts a fast face/non-face classifier at the first stage of cascade face detector. This makes face detection faster and reduces false alarms. For facial color filtering, we define a facial color membership function, and facial color filtering image is obtained using that. An integral image is calculated from facial color filtering image. Using this integral image, its density of subwindow could be obtained very fast. The proposed scanning method skips over sub-windows that do not contain possible faces based on this density. And the face/non-face classifier at the first stage of cascade detector rejects a non-face quickly. By experiment, we show that the proposed face detection model reduces false alarms and is faster than the original cascade face detector.

• Journal of KIISE:Software and Applications
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• v.37 no.12
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• pp.882-891
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• 2010

Many automated dynamic test data generation technique have been proposed. The techniques evaluate fitness of test data through executing instrumented Software Under Test (SUT) and then generate new test data based on evaluated fitness values and optimization algorithms. Previous researches and experiments have been showed that these techniques generate effective test data. However, optimization algorithms in these techniques incur much time to generate test data, which results in huge test case generation cost. In this paper, we propose a technique for reducing the time of evaluating a fitness of test data among steps of dynamic test data generation methods. We introduce the concept of Fitness Evaluation Program (FEP), derived from a path constraint of SUT. We suggest a test data generation method based on FEP and implement a test generation tool, named ConGA. We also apply ConGA to generate test cases for C programs, and evaluate efficiency of the FEP-based test case generation technique. The experiments show that the proposed technique reduces 20% of test data generation time on average.

• Journal of KIISE:Software and Applications
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• v.35 no.5
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• pp.313-324
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• 2008

A sentence reduction is the information compression process which removes extraneous words and phrases and retains basic meaning of the original sentence. Most researches in the sentence reduction have required a large number of lexical and syntactic resources and focused on extracting or removing extraneous constituents such as words, phrases and clauses of the sentence via the complicated parsing process. However, these researches have some problems. First, the lexical resource which can be obtained in loaming data is very limited. Second, it is difficult to reduce the sentence to languages that have no method for reliable syntactic parsing because of an ambiguity and exceptional expression of the sentence. In order to solve these problems, we propose the sentence reduction method which uses templates and POS(part of speech) information without a parsing process. In our proposed method, we create a new sentence using both Sentence Reduction Templates that decide the reduction sentence form and Grammatical POS-based Reduction Rules that compose the grammatical sentence structure. In addition, We use Viterbi algorithms at HMM(Hidden Markov Models) to avoid the exponential calculation problem which occurs under applying to Sentence Reduction Templates. Finally, our experiments show that the proposed method achieves acceptable results in comparison to the previous sentence reduction methods.