• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.3
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• pp.311-317
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• 2013

In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard for applying marine communications in order to multimedia transmission. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed partial memory structure in order to reduced the delay and high speed decoder is possible. The results of the simulation, when the max number of iteration set to 30 times, decoding throughput of HSS algorithm is 326 Mbit/s and decoding speed of proposed algorithm is 2.29 Gbit/s. So, decoding speed of proposed algorithm more than 7 times could be obtained compared to the HSS algorithm.

• The Journal of the Acoustical Society of Korea
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• v.33 no.4
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• pp.262-267
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• 2014

Recently, long pulses are transmitted for target detection in active sonar application. Matched filtering implemented by simple convolution algorithm, requires massive computational power for long replica. The computational loads are reduced significantly by implementing the convolution in the frequency domain with overlap add method, but the performance degrades for specified input/output system delay which constrains the size of FFT function. For performance improvement, the replica could be partitioned into uniform blocks (FDL) by re-using IFFT operations, or variable blocks of increasing length (MC) by using the largest possible blocks to calculate the convolution. In this paper, by combining the strong points of the two methods, we propose a new filter partition structure that allows for further optimization of the previous two methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.9
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• pp.2041-2047
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• 2013

In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed dc-split memory structure in order to reduced the delay and high speed decoder is possible. Finally, this paper presented maximum split memory and throughput for various coding rates in DVB-S2 standard.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.35-44
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• 2002

In this paper, an implementation method of RSA exponentiator based on Radix-$2^k$ modular multiplication algorithm is presented and verified. We use Booth receding algorithm to implement Radix-$2^k$ modular multiplication and implement radix-16 modular multiplier using 2K-byte memory and CSA(carry-save adder) array - with two full adder and three half adder delays. For high speed final addition we use a reduced carry generation and propagation scheme called pseudo carry look-ahead adder. Furthermore, the optimum value of the radix is presented through the trade-off between the operating frequency and the throughput for given Silicon technology. We have verified 1,024-bit RSA processor using Altera FPGA EP2K1500E device and Samsung 0.3$\mu\textrm{m}$ technology. In case of the radix-16 modular multiplication algorithm, (n+4+1)/4 clock cycles are needed and the 1,024-bit modular exponentiation is performed in 5.38ms at 50MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.724-733
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• 2003

Generally, dividers have been designed to use iteration, but recently the research on the pipelined divider is underway. It is a difficult point in the known pipelined division unit that a large lookup table is required. In this paper, the cost-effective pipelined divider is proposed, that needs a lookup table smaller than that of the other pipelined divider. The latency of the proposed divider is 3 cycles. We obtain a 30% reduced area than that of P. Hung.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.3-11
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• 2000

In this paper, we design modular multiplication systolic array and exponentiation processor having n bits message black. This processor uses Montgomery algorithm and LR binary square and multiply algorithm. This processor consists of 3 divisions, which are control unit that controls computation sequence, 5 shift registers that save input and output values, and modular exponentiation unit. To verify the designed exponetion processor, we model and simulate it using VHDL and MAX+PLUS II. Consider a message block length of n=512, the time needed for encrypting or decrypting such a block is 59.5ms. This modular exponentiation unit is used to RSA cryptosystem.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.4B
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• pp.457-462
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• 2001

유/무선 통신 시스템에서는 통신망보다 서로 다른 음성 부호화기를 사용하므로 음성신호는 두 번의 부/복호화과정을 거치게 되어 음질저하, 연산량 증가, 그리고 전달 지연 증가 등의 문제가 발생된다. 본 논문에서는 위의 문제점들을 개선하기 위하여 유/무선 음성통신에 사용되는 음성 부호화기의 상호 부호화 알고리듬을 제안하고, 5.3 kbps G. 723.1의 패킷과 8 kbit/s G.729.A 패킷을 서로 변환하는 방법을 제안한다. 여러 가지 음성 상호 대해 객관적 음질 평가와 주관적 선호도 평가를 수행한 결과, 제안된 상호 부호화 알고리듬이 이중 부/복호화보다 짧은 전달 지연 시간과 26-37% 적은 연산량으로 동등한 음질의 음성신호를 복호화함을 확인하였다.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2224-2227
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• 2003

본 논문에서는 비동기식 3 세대 이동통신망인 WCDMA의 표준 음성 부호화기인 AMR(Adaptive Multi-Rate)[1]과 VoIP(Voice over Internet Protocol) 응용분야에 최근 널리 활용되고 있는 ITU-T 8kbit/s 0.729A[2]의 효율적인 연동을 위한 상호부호화(transcoding) 알고리듬을 제안한다. AMR은 통신 채널 환경에 따라 4.75kbit/s부터 12.2kbit/s까지 가변 하여 통화품질을 보장한다. 따라서, 제안된 상호부호화 알고리듬은 순방향 8 모드, 역방향 8모드를 합하여 총 16모드를 지원한다. 제안된 알고리듬의 성능 평가를 위해 지연 추정, 연산량 측정과 주/객관적 음질평가를 수행한 결과, 제안한 알고리듬은 기존의 tandem보다 최소 5㎳의 짧은 지연, 평균 50.2％의 적은 연산량으로 우수한 음질의 복호화 음성 신호를 제공함을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.6B
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• pp.794-801
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• 2001

본 논문에서는 rank-order 필터의 구현을 위해 세 가지 신경회로망의 구조를 제시하고 분석하며 용도를 제안한다. 첫 번째 신경회로망을 이용하여 2-입력 정렬기를 제안하고 이를 이용하여 계층적인 N-입력 정렬기를 구성한다. 두 번째로 입력 신호간의 상대적인 크기 정보를 이용하여 학습 패턴을 구성한 후 역전파 학습 기법을 이용하여 구현되는 순방향 신경회로망을 이용한 rank-order 필터를 구현한다. 세 번째로 신경회로망의 구조의 출력층에 외부 입력으로 순위 정보를 가지도록 하는 rank-order 필터를 순방향 신경회로망을 이용하여 구현한다. 그리고 이러한 제안된 기술들에 대해 확장성, 구조의 복잡도와 시간 지연 등에서의 성능을 비교, 평가한다. 2-입력 정렬기를 이용하는 방식은 확장이 용이하고 비교적 구조가 간단하나 입력 신호들의 정렬을 위해 신경회로망은 순환하는 구조를 가지며 입력 신호의 수에 비례하는 반복 연산 후에 결과를 얻게 된다. 반면에, 순방향 신경회로망을 이용한 rank-order 필터의 구현 방식은 이러한 반복 연산으로 인한 시간 지연을 줄일 수 있으나 상대적으로 복잡한 구조를 가진다.