• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.256-258
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• 2003

지정 레지스터 수의 증가를 최소화하는 레지스터 할당 방법은 컬러링 과정에서 좀 더 적은 수의 레지스터를 사용하도록 하기 위하여 제안된 방법이다. 이 방법은 생존 범위가 서로 복잡하게 얽혀 있을 때 다른 레지스터 할당 알고리즘 보다 우수한 결과를 보였다. Appel의 간섭 그래프들을 사용하여 제시된 레지스터 할당 방법과 Chaitin의 알고리즘을 비교할 때 500개 이상의 에지를 포함하는 그래프중에 29.7%의 그래프에서 레지스터 요구 수를 적게 요구하였다. 전체 그래프를 대상으로 한 실험에서는 9.7%의 그래프에서 Chaitin의 알고리즘 보다 레지스터를 적게 요구하였고, 노드 병합 레지스터 할당 방법보다는 2.2%의 그래프에서 레지스터 요구수의 감소를 보였다. 제시된 알고리즘은 전역 변수의 사용이 많고, 함수 코드의 길이가 긴 프로그램의 실행 성능 개선에 도움이 될 것으로 예상된다.

• Journal of the Korea Computer Graphics Society
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• v.13 no.4
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• pp.21-27
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• 2007

The 3D Delaunay triangulation is the most widely used method for the mesh creation via the triangulation of a 3D point cloud. However, the method involves a heavy computational cost and, hence, in many interactive applications, it is not appropriate for surface triangulation. In this paper, we propose an efficient triangulation method to create a surface mesh from a 3D point cloud. We divide a set of object points into multiple subsets and apply the 2D Delaunay triangulation to each subset. A given 3D point cloud is cut into slices with respect to the OBB(Oriented Bounding Box) of the point set. The 2D Delaunay triangulation is applied to each subset producing a partial triangulation. The sum of the partial triangulations constitutes the global mesh. As a postprocessing process, we eliminate false edges introduced in the split steps of the triangulation and improve the results. The proposed method can be effectively applied to various image-based modeling applications.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.91-102
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• 2010

It is very difficult that a previous surveillance system and vehicle detection system find objects on a limited and unstable illumination condition. This paper proposes a robust method of adaptively updating a reference background image for solving problems that are generated by the unstable illumination. The first input image is set up as the reference background image, and is divided into three block categories according to an edge component. Then a block state analysis, which uses a rate of change of the brightness, a stability, a color information, and an edge component on each block, is applied to the input image. On the reference background image, neighbourhood blocks having the same state of a updated block are merged as a block. The proposed method can generate a robust reference background image because it distinguishes a moving object area from an unstable illumination. The proposed method very efficiently updates the reference background image from the point of view of the management and the processing time. In order to demonstrate the superiority of the proposed stable manner in situation that an illumination quickly changes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.79-85
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• 2001

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.1
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• pp.60-65
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• 2010

This paper describes the results of 2D mapping, feature detection and matching to create the surrounding environment in the mounted stereo camera on Mobile robot. Extract method of image's feature in real-time processing for quick operation uses the edge detection and Sum of Absolute Difference(SAD), stereo matching technique can be obtained through the correlation coefficient. To estimate the location of a mobile robot using ZigBee beacon and encoders mounted on the robot is estimated by Kalman filter. In addition, the merged gyro scope to measure compass is possible to generate map during mobile robot is moving. The Simultaneous Localization and Mapping (SLAM) of mobile robot technology with an intelligent robot can be applied efficiently in human life would be based.

• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.15-24
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• 1999

In this paper, we propose a new CPLD technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result. it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB.

• Journal of Intelligence and Information Systems
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• v.18 no.2
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• pp.47-60
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• 2012

Video data comes in the form of the unstructured and the complex structure. As the importance of efficient management and retrieval for video data increases, studies on the video parsing based on the visual features contained in the video contents are researched to reconstruct video data as the meaningful structure. The early studies on video parsing are focused on splitting video data into shots, but detecting the shot boundary defined with the physical boundary does not cosider the semantic association of video data. Recently, studies on structuralizing video shots having the semantic association to the video scene defined with the semantic boundary by utilizing clustering methods are actively progressed. Previous studies on detecting the video scene try to detect video scenes by utilizing clustering algorithms based on the similarity measure between video shots mainly depended on color features. However, the correct identification of a video shot or scene and the detection of the gradual transitions such as dissolve, fade and wipe are difficult because color features of video data contain a noise and are abruptly changed due to the intervention of an unexpected object. In this paper, to solve these problems, we propose the Scene Detector by using Color histogram, corner Edge and Object color histogram (SDCEO) that clusters similar shots organizing same event based on visual features including the color histogram, the corner edge and the object color histogram to detect video scenes. The SDCEO is worthy of notice in a sense that it uses the edge feature with the color feature, and as a result, it effectively detects the gradual transitions as well as the abrupt transitions. The SDCEO consists of the Shot Bound Identifier and the Video Scene Detector. The Shot Bound Identifier is comprised of the Color Histogram Analysis step and the Corner Edge Analysis step. In the Color Histogram Analysis step, SDCEO uses the color histogram feature to organizing shot boundaries. The color histogram, recording the percentage of each quantized color among all pixels in a frame, are chosen for their good performance, as also reported in other work of content-based image and video analysis. To organize shot boundaries, SDCEO joins associated sequential frames into shot boundaries by measuring the similarity of the color histogram between frames. In the Corner Edge Analysis step, SDCEO identifies the final shot boundaries by using the corner edge feature. SDCEO detect associated shot boundaries comparing the corner edge feature between the last frame of previous shot boundary and the first frame of next shot boundary. In the Key-frame Extraction step, SDCEO compares each frame with all frames and measures the similarity by using histogram euclidean distance, and then select the frame the most similar with all frames contained in same shot boundary as the key-frame. Video Scene Detector clusters associated shots organizing same event by utilizing the hierarchical agglomerative clustering method based on the visual features including the color histogram and the object color histogram. After detecting video scenes, SDCEO organizes final video scene by repetitive clustering until the simiarity distance between shot boundaries less than the threshold h. In this paper, we construct the prototype of SDCEO and experiments are carried out with the baseline data that are manually constructed, and the experimental results that the precision of shot boundary detection is 93.3% and the precision of video scene detection is 83.3% are satisfactory.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.224-234
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• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that if fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs bu 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.9-17
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• 1999

In this paper, we propose a new technology mapping algorithm for CPLD under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces delay time and the number of CLBs much more than the existing tools of technology mapping algoritm.

• Journal of Broadcast Engineering
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• v.16 no.1
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• pp.44-53
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• 2011

In this paper, we propose a 3D conversion algorithm of 2D video using depth layer partition method. In the proposed algorithm, we first set frame groups using cut detection algorithm. Each divided frame groups will reduce the possibility of error propagation in the process of motion estimation. Depth image generation is the core technique in 2D/3D conversion algorithm. Therefore, we use two depth map generation algorithms. In the first, segmentation and motion information are used, and in the other, edge directional histogram is used. After applying depth layer partition algorithm which separates objects(foreground) and the background from the original image, the extracted two depth maps are properly merged. Through experiments, we verify that the proposed algorithm generates reliable depth map and good conversion results.