• The Journal of the Korea Contents Association
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• v.11 no.9
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• pp.45-53
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• 2011

According to the necessity of measuring equipments for advanced military systems, real-time characteristics such as time determinism and execution accuracy pursuing low-latencies have become very important. With this reason, the market demand for real-time features in the general purpose operating system such as Linux has been enlarging. To meet these requirements, RTLinux and RTAI has been developed as dual-kernels based on Linux. However, developers should use assembler languages to facilitate real-time in RT-Linux, it is very difficult to deal with it. RTAI has disadvantage that it only provides soft real-time. To solve these problems, RTiK-Linux was developed. In this paper, we propose a new dual-kernel with hard real-time capabilities in Linux, called RTiK-Linux(Real-Time implemented Kernel for Linux). We first introduce related researches and then describe the design methodologies to guarantee the resolution which almost accords with the timer settings. Finally, we present the results of experimental measurements and analyze them in order to validate and evaluate the proposed RTiK-Linux.

• Journal of Korea Multimedia Society
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• v.8 no.9
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• pp.1282-1291
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• 2005

This paper presents the EVM(Embedded Virtual Machine) which enables the execution of dynamic applications loaded in the embedded systems such as Mobile Devices(mobile phone, PDA), Set-Top Box, and Digital TV using downloading techniques. To accomplish this goal, we defined a SIL-(Standard Intermediate Language) code, and implemented a Bytecode-to-SIL translator which enables the execution of programs written in java language in the EVM platform without JVM, and a MSIL--to-SIL- translator which enables for programs written in .NET language to be executed in the EVM platform without .NET platform. Also, we developed a EFF(Executable File Format) builder as an assembler which translates SIL codes into an executable file, *.evm, and implemented the EVM which reads the *.evm file and executes it. The virtual machine for embedded systems developed in this paper is the software technologies that enable the execution of applications or contents without changes to when the platforms change. In fact, the virtual machine suggested here is not only usable as a standard model for existing virtual machines but also aid in more efficient execution of applications loaded in the embedded systems such as Mobile Devices, Digital TV, and Set-Top Box.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.1
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• pp.53-59
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• 2009

By the use of open source and 16bit Microcomputer, IDB(Integrated Development Board) for embedded technical education was designed and developed. Based on 16bit MCU H8/300H, LED, LED Matrix, motors, sensors and various I/O circuitry, and the connection to a computer via the SCI, and $16{\times}2$ character LCD was designed and implemented on IDB. In addition, the software development environment was build by the assembler and H8 C compiler which is provided to the open-source software. And memory expansion was considered to include TRON(Real time OS) and uClinux. To verify the developed board, IDB was fabricated by PCB machine, and the fuction was confirmed by the basic I/O control program.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.29-42
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• 1990

In this paper, We use the APL as IDL when simulation a 16-bit SIP. It was possible for IDL to represent and describe a structure of a H/W which other HDL have not. Because We partitioned whole system to various modules when desingning processor, We adpoted a direct decoding method. A designed each modules are executed according to 12-bit control word was inputed through experimental framework, Which were composed to symbolized instructions. In here, By setting instruction codes of the SIP using binary code, We composed instruction format and assembler instruction, and verified the SIP behaviour that try to implement by entering a presented instruction set through experimental framework. In a presented SIP, Because inputing program are a symbolized language, Designer and user will easily understand behaviour of system. Especially, Because we can immediatly specify a unit function within SIP, We will use variously and easily the library cell.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.520-528
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• 2000

he speed of microprocessor getting faster, the data transfer width between the microprocessor and the memory becomes a critical part to limit the system performance. So the study of the computer architecture with the high code density is cmerged. In this paper, a tentative Bi-Length Instruction Set Computer(BISC) that consists of 16 bit and 32 bit length instructions is proposed as the high code density 32 bit microprocessor architecture. The 32 bit BISC has 16 general purpose registers and two kinds of instructions due to the length of offset and the size of immediate operand. The proposed 32 bit BISC is implemented by FPGA, and all of its functions are tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit BISC are designed and verified. This paper also proves that the code density of 32 bit BISC is much higher than the one of traditional architecture, it accounts for 130~220% of RISC and 130~140% of CISC. As a consequence, the BISC is suitable for the next generation computer architecture because it needs less data transfer width. And its small memory requirement offers that it could be useful for the embedded microprocessor.

• Journal of Korea Multimedia Society
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• v.3 no.2
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• pp.192-200
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• 2000

8 bit and 16 bit microprocessors are widely used in the small sited control machine. The embedded microprocessors which is integrated on a single chip with the memory and I/O circuit must have simple hardware circuit and high code density. This paper proposes a 16 bit high code density EISC(Extendable Instruction Set Computer) microprocessor. SE1608 has 8 general purpose registers and 16 bit fixed length instruction set which has the short length offset and small immediate operand. By using an extend register and extend flag, the offset and immediate operand in instruction could be extended. SE1608 is implemented with 12,000 gate FPGA and all of its functions have been tested and verified at 8MHz. And the cross assembler, the cross C/C++compiler and the instruction simulator of the SE1608 have been designed and verified. This paper also proves that the code density$.$ of SE1608 shows 140% and 115% higher code density than 16 bit microprocessor H-8300 and MN10200 respectively, which is much higher than traditional microprocessors. As a consequence, the SE1608 is suitable for the embedded microprocessor since it requires less program memory to any other ones, and simple hardware circuit.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.5
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• pp.486-497
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• 2001

In this paper, we propose a new addressing mode, which can be used for programmable image processor to perform image-processing algorithms effectively. Conventional addressing modes are suitable for one-dimensional data processing such as voice, but the proposed addressing mode consider two-dimensional characteristics of image data. The proposed instruction for two-dimensional addressing requires two operands to specify a pixel and doesn't require any change of memory architecture. The proposed two-dimensional addressing mode for image processor has the following advantages. The proposed instruction combines several instructions to load a pixel data from an external memory to a register. Hence, the proposed instruction reduces required code size so that it satisfies high performance and low power requirements of image processor. In addition, it uses inherent two-dimensional characteristics of image data and offers user-friendly instruction to assembler programmer The proposed two-dimensional addressing mode is applicable to DSP, media processor, graphic device, and so on. In this paper, we propose a new concept of two-dimensional addressing mode and an efficient hardware implementation method of it.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.11-20
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• 1999

The data transfer width between the mocroprocessor and the memory comes to a critical part that limits system performance since the data transfer width has been as it was while the performance of a microprocessor is getting higher due to its continuous development in speed. And it is important that the memory should be in small size for the reduction of embedded microprocessor's price which is integrated on a single chip with the memory and IO circuit. In this paper, a mocroprocessor tentatively named as Extendable Instruction Set Computer(EISC) is proposed as the high code density 32 bit mocroprocessor architecture. The 32 bit EISC has 16 general purpose registers and 16 bit fixed length instruction which has the short length offset and small immediate operand. By using and extend register and extend flag, the offset and immediate operand could be extended. The proposed 32 bit EISC is implemented with an FPGA and all of its functions have been tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit EISC shows 140-220% and 120-140% higher code density than RISC and CISC respectively, which is much higher than any other traditional architectures. As a consequence, the EISC is suitable for the next generation computer architecture since it requires less data transfer width compared to any other ones. And its lower memory requirement will embedded microprocessor more useful.