• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.48 no.1
• /
• pp.25-31
• /
• 2011

In the underwater communications, transmitted acoustic signal is corrupted by interference from multipath. A parametric array transducer is capable of radiating a narrow beam with very low sidelobe levels. In certain cases, the parametric array transducer can help the multipath problem. To improve the performance of the underwater communications, the statistical signal processing methods will be required. In the paper, the communication system using a parametric array transducer was demonstrated. To detect the received signal of the communication system based on the on-off keying, the maximum likelihood method using averaged signal for a particular window size is used. The communication system has GUI using LebVIEW which allows the user to change the parameter. The GUI can also be easily modified based on the characteristics of a parametric array transducer. The implemented system can effectively evaluate the performance of the parametric array transducer.

• The Journal of the Acoustical Society of Korea
• /
• v.11 no.3
• /
• pp.53-60
• /
• 1992

Many adaptive beamforming methods have been studied for interference cancellation and speech signal enhancement in telephone conference and auditorium. Main aspect of adaptive beamforming methods for speech signal processing is different from radar, sonar and seismic signal processing because desire output signal should be apt to the human ear. Considering that phase of speech is quite insensible to the human ear, Sondhi proposed a nonlinear constrained optimization technique whose constraint was on the magnitude transfer function from the source to the output. In real environment the phase response of the speech signal affects the human auditorium system. So it is desirable to design linear phase system. In this paper, linear phase beamformer is proposed and sample processing algorithm is also proposed for real time consideration Simulation results show that the proposed algorithm yields more consistent beam patterns and deep nulls to the noise direction than Sondhi's.

• Proceedings of the KIEE Conference
• /
• 2015.07a
• /
• pp.1381-1382
• /
• 2015

본 논문에서는 초음파 수신기 어레이 및 아날로그 신호처리부로 구성된 스트랩다운 측위센서를 이용하여 특정 위치에 장착되어 있는 송신기와 로봇 간 상대위치를 측정할 수 있는 새로운 형태의 자율주행로봇 보조항법 시스템을 제안한다. 이를 이용하여 상태변수 간의 기하학적 상관관계를 활용하여 십자형으로 배열된 다중센서 기반 피동 위치추정 필터 구현에 사용되는 설계변수의 불완전성을 보상하는 방법을 제안한다. 모의실험을 통해 제안한 방법의 유용성을 검증한다.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.39 no.9
• /
• pp.896-903
• /
• 2011

In this paper, a co-design method for JPEG2000 video compression system using DSP and FPGA is presented. By profiling the complexity of JPEG2000 algorithm, it is noticed that a MQ-coder is the most complex part. Thus, we implement the MQ-coder on FPGA for the parallel processing using VHDL to reduce the complexity. In order to verify the performance of the MQ-coder, JBIG2 standard test vector and images are used. The experimental results show that the proposed MQ-coder enhances the processing time approximately 3 times compared with the previous software MQ-coder.

• Journal of Sensor Science and Technology
• /
• v.8 no.6
• /
• pp.461-468
• /
• 1999

In this paper, we have implemented a gas recognition system for classification and identification of explosive gases such as methane, propane, and butane using a sensor array and an artificial neural network. Such explosive gases which can be usually detected in the oil factory and LPG pipeline are very dangerous for a human being. We analyzed the characteristics of a multi-dimensional sensor signals obtained from the nine sensors using the principal component analysis(PCA) technique. Also, we implemented a gas pattern recognizer using a multi-layer neural network with error back propagation learning algorithm, which can classify and identify the sorts of gases and concentrations for each gas. The simulation and experimental results show that the proposed gas recognition system is effective to identify the explosive gases. And also, we used DSP board(TMS320C31) to implement the proposed gas recognition system using the neural network for real time processing.

• Journal of the Institute of Convergence Signal Processing
• /
• v.19 no.3
• /
• pp.89-96
• /
• 2018

This study aims to develop a fully passive smart sensing tag utilizing RF (Radio Frequency) energy harvesting technology at UHF (Ultra High Frequency) band of 915MHz. To optimize the power collected under various radiated conditions, an efficient energy harvesting module exploiting a boost circuit with maximum power point tracking (MPPT) is employed. Specifically, the proposed tag features two orthogonal antennas to enhance its capability of both energy scavenging and data transmissions. The experimental result shows that the developed smart sensor tag can scavenge an RF input power of as low as 0.19mW at a distance of 4 meters for a 3.6Vdc output. Furthermore, the proposed smart sensor tag performs the feasibility of completely autonomous monitoring food freshness at 2 meters with a low-power sensor array.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.10C
• /
• pp.984-994
• /
• 2003

This paper proposes a novel blind adaptive algorithm for computing the weight vector of an antenna array system. The new technique utilizes a Generalized On-Off algorithm to obtain the weight vector maximizing the SINR(Signal to Interference plus Noise Ratio) of the received signal. It is observed that the proposed algorithm generates a suboptimal weight vector with a linear computational load(O(6N+8)). From the various simulations, it is confirmed that, when the signal environment becomes adverse, e.g., low Processing Gain, and/or wide angular spread. the proposed algorithm outperforms the conventional one in terms of the communication capacity by about 3 times. Applying the proposed algorithm to satellite tracking systems as well as IS2000 1X mobile communication system, we have found that both communication capacity and communication quality are significantly improved.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.37 no.5
• /
• pp.93-102
• /
• 2000

This paper describes the architecture and characteristics of the satellite modem unit (SMU) developed for the DAMA-SCPC Ground System(DGS), which is a Demand Assignment Multiple Access-Single Channel per Carrier (DAMA-SCPC) satellite network. There are several requirements for the SMU from the system architecture and design concept. To meet these requirements the SMU was designed and implemented by extensively applying digital signal processing (DSP) technique and field programmable gate array (FPGA). The developed SMU met the functional and performance requirements, and has been working well. The measured BER was about 1 $\times$10E-4 in continuous mode(at Eb/No=4.7, FEC=3/4).

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.4C
• /
• pp.342-349
• /
• 2008

This paper presents a new digit-serial systolic multiplier over $CF(2^m)$ for cryptographic applications. When input data come in continuously, the proposed array produces multiplication results at a rate of one every ${\lceil}m/D{\rceil}$ clock cycles, where D is the selected digit size. Since the inner structure of the proposed array is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementations.

• The KIPS Transactions:PartA
• /
• v.15A no.3
• /
• pp.161-166
• /
• 2008

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF($2^m$) using the polynomial basis representation. The proposed systolic array is based on the most significant digit first (MSD-first) multiplication algorithm and produces multiplication results at a rate of one every "m/D" clock cycles, where D is the selected digit size. Since the inner structure of the proposed multiplier is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of a high regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.