• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.3
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• pp.591-596
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• 2001

In recent years, interest in microstrip antenna has been increasing, primarily because of their low profile, and light weight and relative cheapness. In this paper we present a theoretical analysis of the circular Patch array antenna. The theory is based on cavity model analysis. The calculated results are compared with experimental results showing good agreement. A $8\times8$ array antenna at 12GHz frequency band is designed and tested. The experimental results of relatively good characteristics show that its maximum rain is 24.8(dB), and its impedance bandwidth is 120MHz$(VSWR\leq2)$.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.48-50
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• 1999

본 논문에서는 비선형 편집기를 위해 구현한 디스크 어레이의 구조[1][2][3]에서 편집할 영상의 특성에 따라 최적의 시스템을 구현하는 방법을 성능 분석에 의해 제시한다. 비선형 편집기를 위한 디스크 어레이는 여러 노드로 구성되어 영상의 종류에 따라 확장성이 용이하며 각 노드는 2개의 SCSI버스에 14개의 디스크가 연결 가능하다. 이러한 구조의 시스템에서 디스크의 개수 및 노드의 수를 이용한 SCSI버스의 성능 분석 모델을 제시한다. 성능 분석은 노드 수 및 디스크의 개수에 따라 SCSI 버스의 대역폭 및 디스크들의 검색 속도 비교 후 느린 부분을 찾도록 한다. 주어진 요구에 맞는 시스템을 설계하기 위해 성능 분석 모델을 이용한 최적의 자원을 갖는 비선형 편집 시스템 구현 방법을 제시하며 이를 이용한 무압축 NTSC 비선형 편집기의 설계 및 구현 예를 보인다.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.4 no.2
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• pp.34-40
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• 1993

A microstrip antenna for mobile system are designed at the resont frequency 0.88 GHz. The microstrip array antenna are designed to depend on the size of rectanular microstrip path for the relative current distribution to be 1:4.69:1 using Tchebyscheff polynominals. Gain difference between the main lobe and sidelobe is calculated for theoritical values of 20 dB. The designed microstrip array antenna are mesureed various characteristics, such as return loss, radiation pattern, V.S.W.R, bandwidth, and agreed with each other and theoretical value. Also it is presented a process of phase variation of patch array antenna depend on relative current distribution for beam scanning.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.37-44
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• 2002

This paper proposes efficient digital hardware design method by using fixed weight of pre-trained neural network. For this, arithmetic operations of PEs(Processing Elements) are represented with matrix-vector multiplication. The relationship of fixed weight and input data present bit-level array structure architecture which is consisted operation node. To minimize the operation node, this paper proposes node elimination method and setting common node depend on bit pattern of weight. The result of FPGA simulation shows the efficiency on hardware cost and operation speed with full precision. And proposed design method makes possibility that many PEs are implemented to on-chip.

• Aerospace Engineering and Technology
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• v.1 no.1
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• pp.72-83
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• 2002

Required power and solar array sizing of KOMPSAT-2 have been analyzed by ASTRIUM and KARI in November, 2000. There are Electrical Power Subsystem(EPS) design discrepancies between ASTRIUM and Korea Aerospace Research Institute(KARI) according to heritage program, EPS operation concepts, power source and the characteristic of the electrical boxes. To design the power system of KOMPSAT-2, ASTRIUM has used the EPS design of the CHAMP and GlobalStar program. But SSTI, TOMS-EP and KOMPSAT-1's design concepts has been used for KOMPSAT-2 EPS design by the KARI. To get the design conclusion, there are many trade-off meetings for the EPS sizing using each sides' heritage program and EPS operation concept. And the EPS design factors and approaching methods have been reviewed and discussed. In addition the EPS design results from ASTRIUM and KARI are summarized in this paper.

• The Journal of the Korea Contents Association
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• v.14 no.10
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• pp.1-9
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• 2014

Generally, integral image used for autostereoscopic 3d display is generated for flat lens array, but flat lens array cannot provide a wide range of view for generated integral image because of narrow range of view. To make up for this flat lens array's weak point, curved lens array has been proposed, and due to technical and cost problem, approximate surface lens array composed of several flat lens array is used instead of ideal curved lens array. In this paper, we constructed an approximate surface lens array arranged for $20{\times}8$ square flat lens in 100mm radius sphere, and we could get about twice angle of view compared to flat lens array. Specially, unlike existing researches which manually generate integral image, we propose an OpenCL GPU parallel process algorithm for generating real-time integral image. As a result, we could get 12-20 frame/sec speed about various 3D volume data from $15{\times}15$ approximate surface lens array.

• Journal of the Korea Society of Computer and Information
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• v.19 no.10
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• pp.71-79
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• 2014

In this paper, the microstrip array antenna is studied to replace the parabolic antenna in the direct satellite reception. A microstrip array antenna has been used in extremely limited area, but if it is applied to practical life like a direct satellite reception antenna, we expect that it will be used in various way. First of all, if we use a microstrip array antenna for a direct satellite reception antenna, it should be guaranteed characteristics of broadband frequency. Therefore, the goal of this paper is designing technique an antenna which guarantees broadband frequency band for a direct satellite reception. In this paper, the proposed microstrip antenna is fed by orthogonal two feed lines to a rectangular patch and a sequentially rotated feeding technique is designed proposed for a good axial ratio in broadband frequency band. The rectangular patch is designed to satellite reception band, and the width and length are W=L=8.9 mm ($0.352{\lambda}o$) respectively. The antenna's ground plane has dimensions of $250{\times}250mm$. The experimental results verify that the proposed antenna had the axial ratio of above 1dB broader than that of the conventional feeding antenna. In order to verify the performance, a $8{\times}8$ array having two pairs was fabricated and tested. The maximum gain is 20.8 dB, the sidelobe level confirm less than -10 dB. It is verified by link budget calculation that C/N=6.7 dB can be obtained for domestic use if this proposed antenna is used in Koreasat reception system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.9
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• pp.1055-1063
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• 1999

공개키 암호화 시스템에서 주된 연산은 512비트 이상의 큰 수에 의한 모듈러 지수 연산으로 표현되며, 이 연산은 내부적으로 모듈러 곱셈을 반복적으로 수행함으로써 계산된다. 본 논문에서는 Montgomery 알고리즘을 분석하여 right-to-left 방식의 모듈러 지수 연산에서 공통으로 계산 가능한 부분을 이용하여 모듈러 제곱과 모듈러 곱셈을 동시에 수행하는 선형 시스톨릭 어레이를 설계한다. 설계된 시스톨릭 어레이는 VLSI 칩과 같은 하드웨어로 구현함으로써 IC 카드나 smart 카드에 이용될 수 있다.Abstract The main operation of the public-key cryptographic system is represented the modular exponentiation containing 512 or more bits and computed by performing the repetitive modular multiplications. In this paper, we analyze Montgomery algorithm and design the linear systolic array for performing modular multiplication and modular squaring simultaneously using the computable part in common in right-to-left modular exponentiation. The systolic array presented in this paper could be designed on VLSI hardware and used in IC and smart card.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.7
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• pp.743-751
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• 1999

공개키 암호 시스템에서 모듈러 지수 연산은 주된 연산으로, 이 연산은 내부적으로 모듈러 곱셈을 반복적으로 수행함으로써 계산된다. 본 논문에서는 GF(2m)상에서 수행할 수 있는 Montgomery 알고리즘을 분석하여 right-to-left 방식의 모듈러 지수 연산에서 공통으로 계산 가능한 부분을 이용하여 모듈러 제곱과 모듈러 곱셈을 동시에 수행하는 선형 시스톨릭 어레이를 설계한다. 본 논문에서 설계한 시스톨릭 어레이는 기존의 곱셈기보다 모듈러 지수 연산시 약 0.67배 처리속도 향상을 가진다. 그리고, VLSI 칩과 같은 하드웨어로 구현함으로써 IC 카드에 이용될 수 있다.Abstract One of the main operations for the public key cryptographic system is the modular exponentiation, it is computed by performing the repetitive modular multiplications. In this paper, we analyze Montgomery's algorithm and design a linear systolic array to perform modular multiplication and modular squaring simultaneously. It is done by using common-multiplicand modular multiplication in the right-to-left modular exponentiation over GF(2m). The systolic array presented in this paper improves about 0.67 times than existing multipliers for performing the modular exponentiation. It could be designed on VLSI hardware and used in IC cards.