• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.67-74
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• 2000

In this paper, a $54{\times}54$-bit multiplier based on a improved conditional sum adder is proposed. To reduce the multiplication time, high compression-rate compressors without Booth's Encoding, and a 108-bit conditional sum adder with separated carry generation block, are developed. Furthermore, a design technique based on pass-transistor logic is utilized for optimize the multiplication time and the power consumption by about 5% compared to that of conventional one. With $0.65{\mu}m$, single-poly, triple-metal CMOS process, its chip size is $6.60{\times}6.69\;mm^2$ and the multiplication time is 135.ns at a 3.3V power supply.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2002.11a
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• pp.63-68
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• 2002

JPEG2000은 기존의 정지영상압축부호화 방식에 비해 우수한 비트율-왜곡(Rate-Distortion)특성과 향상된 주관적 화질을 제공하며 인터넷, 디지털 영상카메라, 이동단말기, 의학영상 등 다양한 분야에서 적용될 수 있는 새로운 정지영상압축 표준이다. 본 논문에서는 SoC(System on a Chip)설계를 고려한 JPEG2000 인코더의 구조를 제안하고 IP(Intellectual Property)를 설계 및 검증하였다. 구현된 JPEG2000 IP는 DWT(Discrete Wavelet Transform)블록, 스칼라양자화블록, EBCOT(Embedded Block Coding with Optimized Truncation)블록으로 구성되어 있다. IP는 모의실험을 통해 구현 구조에 대한 타당성을 검증하였고, 반도체설계자산연구센터에서 제시한 'RTL Coding Guideline'에 따라 HDL을 설계하였다. 특히, DWT블록은 구현시 많은 연산과 메모리 용량이 필요하므로 영상을 저장할 외부 메모리를 사용하였고, 빠른 곱셈과 덧셈연산을 위한 3단 파이프라인 부스곱셈기(3-state pipeline booth multiplier)와 캐리예측 덧셈기(carry lookahead adder)를 사용하였다. 설계된 JPEG2000 IP들은 삼성 0.35$\mu\textrm{m}$ 라이브러리를 이용하여 Synopsys사 Design Analyzer 틀을 통해 논리 합성하였으며, Xillinx 100만 게이트 FPGA칩에 구현하여 그 동작을 검증하였다. 또한, Hard IP 설계를 위해 Avanti사의 Apollo툴을 이용하여 Layout을 수행하였다.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.37-45
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• 2008

In this study, reliabilities of Cu (60 um)/SnAg (20 um) double-bump flip chip assemblies were investigated for the flip chip interconnections on organic substrates with 100 um pitch. After multiple reflows at $250^{\circ}C\;and\;280^{\circ}C$, bump contact resistances were almost same regardless of number of reflows and reflow temperature. In the high temperature storage test, there was no bump contact resistance change at $125^{\circ}C$ up to 2000 hours. However, bump contact resistances slightly increased at $150^{\circ}C$ due to Kirkendall voids formation. In the electromigration test, Cu/SnAg double-bump flip chip assemblies showed no electromigration until about 600 hours due to reduced local current density. Finally, in the thermal cycling test, thermal cycling failure mainly occurred at Si chip/Cu column interface which was found out the highest stress concentration site in the finite element analysis. As a result, Al pad was displaced out under thermal cycling. This failure mode was caused by normal compressive strain acting Cu column bumps along perpendicular direction of a Si chip.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.11
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• pp.2543-2551
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• 1997

This paper proposes a compression technique of image data, a variable length PN code and channel models which are required in CDMA communication system. It also analyzes their performances. Original images is compressed by 2-D DCT and its coefficients are quantized by optimal quantizer at compression rate 0.84bit/pel. Channel model 1 and 2 which are composed of 5 and 4 channels respectively are employed to be used in CDMA. Such a situation forces us to empoly variable length PN code, such as Chebyshev map for spread spectrum system. When average PN code length of model 1 and 2 is 44.4 and 26.7 chips respectively, the received image through these models under Gaussian noise with variance 1.75 is visually of the same quality as the transmitting image. Thus, the model 2 appears to be better in channel efficiency, comparing with channel model 1 and channel model which uses fixed length PN code.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.335-344
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• 2003

The image compression based on discrete wavelet transform has been widely accepted in industry since it shows no block artifacts and provides a better image quality when compressed to low bits per pixel, compared to the traditional JPEG. The coefficients generated by discrete wavelet transform are quantized to reduce the number of code bits to represent them. After quantization, lossless coding processes are usually applied to make further reduction. This paper presents a new and efficient lossless coding algorithm for quantified wavelet coefficients based on the statistical properties of the coefficients. Combined with discrete wavelet transform and quantization processes, our algorithm has been implemented as an image compression chip, using 0.5${\mu}{\textrm}{m}$ standard cells. The experimental results show the efficiency and performance of the resulting chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.26-31
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• 2009

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.11b
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• pp.421-424
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• 2002

본 연구에서는 ARM720T core를 사용한 보드에서 머리 전달 함수(HRTF)를 이용한 입체음향 시스템을 구현하였다. ARM720T core를 탑재한 EP7312칩은 저전력 고성능 프로세서로서의 이점을 갖고 있기 때문에 HRTF의 특성을 이용한 입체음향 실시간 구현이 가능하다. 또한 ARM 프로세서를 사용함으로, DAC제어부 부분을 제외한 메인 프로세싱 부분은 ARM 계열의 다른 프로세서에서도 쉽게 사용 가능하단 이점이 있다. HRTF를 이용하여 2채널의 입체음향을 구현하는 방식은 콘볼루션에서 많은 계산량이 소요된다. 본 연구에서는 실시간 구현 시 계산량을 줄이기 위해 시간영역의 콘볼루션을 사용하지 않고 주파수 영역에서의 가중 중복 합산방식을 이용하여 계산하였다. 본 연구의 연구 결과는 가상현실이나 방송음향장비 뿐만 아니라 저전력을 요구하는 휴대용 멀티미디어 기기에서 MP3/AAC/WMA와 같은 오디오 압축 장치부분에 활용되어 질 수 있다.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05b
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• pp.1097-1100
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• 2003

본 논문에서는 최근 유선을 대치하기 위해 등장한 여러 가지 근거리 무선통신 방식 중 블루투스 기술과 시스템의 안정성 및 리소스의 효율적 사용을 위한 멀티태스킹이 가능한 RTOS(uC/OS)를 이용하여 투선 비디오 도어폰을 설계 및 구현해 본다. 송신기는 카메라, 비디오 디코더, 영상 압축칩 프로세서(ARM7TDMI), 메모리, 블루투스 모듈 등을 이용하여 임베디드 시스템을 구성하였고, 수신기는 블루투스 모듈을 통해 수신된 영상 데이터를 모니터에 디스플레이 할 수 있다.

• Journal of the Korean Society for Precision Engineering
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• v.30 no.3
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• pp.278-283
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• 2013

While Built-in Spindle is working in machining center, the tool is changed by ATC(Automatic Tool Changer) automatically. However, impurities could be stacked in front of spindle because of chips formation while machining, and positional error between spindle and tool could be generated. Compressed air holes are necessary for removal of the impurities. But, the diameter and number of compressed air hole are different for each built-in spindle in market. In this paper, flow analysis is carried out to find out the efficient figuration of the compressed air hole by using velocity and pressure distributions.