• Journal of KIISE:Computer Systems and Theory
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• v.34 no.11
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• pp.581-588
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• 2007

In Digital Right Management, symmetric cipher is used for content encryption to reduce encryption cost, AES, advanced encryption standard is usually used to multimedia encryption under desktop environment because of its reasonable security level and computation cost. But mobile handheld device often uses slow speed processor and operates under battery-powered environment. Therefore it requires low computation cost and low energy consumption. This paper proposes new stream cipher scheme which combines pseudo random number generator(PRNG) and dynamically generated permutations. Proposed scheme activates PRNG and generates original key streams. Then it generates extended key streams by applying permutation to original sequence. These extended key streams are XORed with plaintext and generate ciphertext. Proposed scheme reduces the usage of PRNG. Therefore this scheme is fast and consumes less energy in comparison with normal stream cipher. Especially, this scheme shows great speed up (almost 2 times) than normal stream cipher scheme in random access.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10c
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• pp.626-628
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• 2006

본 논문에서는 Pipeline 기법을 이용한 고속 암호 프로세서의 설계 및 구현에 관하여 기술한다. 암호화를 위한 알고리듬은 DES 와 SEED를 사용하고 인증을 위한 알고리듬은 HMAC-SHA-1을 이용한다. 제안된 암호 프로세서는 VHDL을 사용하여 구조적 모델링을 행하였으며, Xilinx사의 ISE 6.2i 툴을 이용하여 논리 합성을 수행하였다. 설계 검증을 위해 Modelsim을 이용하여 타이밍 시뮬레이션을 수행하여, 설계된 시스템이 정확히 동작함을 확인하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.1117-1120
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• 2007

본 논문에서는 개선된 F함수를 이용 하여 국내 표준 128비트 블록 암호화 알고리듬인 SEED 암호 프로세서의 FPGA 구현에 관하여 기술한다. 제안한 SEED 암호 프로세서는 Verilog-HDL를 사용하여 구조적 모델링을 하였으며, Xilinx사의 ISE 9.1i 툴을 이용하여 논리 합성을 수행하였다. 설계 검증은 Modelsim 6.2c 툴을 이용하여 타이밍 시뮬레이션을 수행하였으며, FPGA Prototype 시스템을 사용하여 설계된 하드웨어 동작을 검증하였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.3
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• pp.3-9
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• 2011

In this paper, we propose workload partitioning methods in parallelizing AES-CCM which is proposed as the wireless encryption and message integrity standard IEEE 802.11i. In parallelizing AES-CCM having data dependency, synchronizations among processors are required, and multi-core processors have a very large range of synchronization performance. We propose and compare the performance of various workload partitioning methods by considering both the computational characteristics of AES-CCM and the synchronization overhead.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.401-403
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• 2015

This paper describes an efficient hardware design of 128-bit block cipher algorithm LEA(lightweight encryption algorithm). In order to achieve area-efficient and low-power implementation, round block and key scheduler block are optimized to share hardware resources for encryption and decryption. The key scheduler register is modified to reduce clock cycles required for key scheduling, which results in improved encryption/decryption performance. FPGA synthesis results of the LEA processor show that it has 2,364 slices, and the estimated performance for the master key of 128/192/256-bit at 113 MHz clock frequency is about 181/162/109 Mbps, respectively.

• Journal of the Korea Society of Computer and Information
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• v.12 no.2 s.46
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• pp.63-70
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• 2007

The Data Encryption Standard (DES) is a block cipher that encrypts a 64 bit block of plaintext into a 64 bit block of ciphertext. The DES has been a worldwide standard for 20 years since it was adopted in 1976. strong. But, due to the rapid development of hardware techniques and cryptanalysis, the DES with 64-bit key is considered to be not secure at the present time. Therefore it became necessary to increase the security of DES. The NG-DES(New Generation DES)[1] is an encryption system which upgrades the encryption security of DES by the key extension and the usage of non-linear f function. It extends not only the size of plaintext and ciphertext to 128 bit but also the Fiestel structure used in each round. This structure has a weak point that the change of each bit of plaintext does not affect all bits of ciphertext simultaneously. In this paper, we propose a modified Fiestel structure of DES and thus increased confusion and diffusion by effectively cross-connecting between outputs in a round and inputs in next round.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.1
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• pp.75-80
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• 2009

RSA cryptoprocessors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, a fast 32bit modular multiplier which is required to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The proposed architecture prototype of the multiplier unit was automatically synthesized, and successfully operated at the frequency in the target RSA processor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.740-743
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• 2008

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, $32b^*32b$ multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the stalks flag. In this paper, a fast 32bit nodular multiplier which is required to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The proposed architecture prototype of the multiplier unit was automatically synthesized, and successfully operated at the frequency in the target RSA processor.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.3
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• pp.85-90
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• 2003

This paper proposes a modular multiplier based on LFSR (Linear Feedback Shift Register) architecture with efficient area complexity over GF(2/sup m/). At first, we examine the modular exponentiation algorithm and propose it's architecture, which is basic module for public-key cryptosystems. Furthermore, this paper proposes on efficient modular multiplier as a basic architecture for the modular exponentiation. The multiplier uses AOP (All One Polynomial) as an irreducible polynomial, which has the properties of all coefficients with '1 ' and has a more efficient hardware complexity compared to existing architectures.