• Review of KIISC
• /
• v.16 no.3
• /
• pp.63-74
• /
• 2006

본 논문에서는 한국 산업규격 KS 표준 블록암호 알고리즘인 ARIA의 핵심논리들을 64비트 프로세서 환경에서 효율적으로 구현하는 방법을 제안하고, 제안된 방법으로 구현된 ARIA를 대표적인 64비트 마이크로프로세서인 Intel Pentium4 x64, Intel Itanium, Intel XEON(EM64T)을 이용하여 그 효율성을 평가하였으며, 32비트 프로세서에 적합하게 구현된 ARIA와 효율성을 비교하고 문제점을 분석하였다.

• Journal of Internet Computing and Services
• /
• v.21 no.3
• /
• pp.11-19
• /
• 2020

In this paper, a merged TEA block cipher processor which unifies Tiny Encryption Algorithm(TEA), extended Tiny Encryption Algorithm(XTEA) and corrected block TEA(XXTEA) is designed. After TEA cipher algorithm was first designed, XTEA and XXTEA cipher algorithms were designed to correct security weakness. Three types of cipher algorithm uses a 128-bit master key. The designed cipher processor can encrypt or decrypt 64-bit message block for TEA/XTEA and variable-length message blocks up to 256-bit for XXTEA. The maximum throughput for 64-bit message blocks is 137Mbps and that of 256-bit message blocks is 369Mbps. The merged TEA block cipher designed in this paper has a 16% gain on the area side compared to a lightweight LEA cipher. The cryptographic IP of this paper is applicable in security module of the mobile areas such as smart card, internet banking, and e-commerce.

• KIPS Transactions on Computer and Communication Systems
• /
• v.8 no.11
• /
• pp.271-276
• /
• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.15 no.5
• /
• pp.3-11
• /
• 2005

This paper presents a performance analysis model based on an M/M/1 queue and Poisson distribution of input data traffic. The simulation on a pipelined AES system with processing rate of 10 rounds per clock shows $4.0\%$ higher performance than a non-pipelined version consuming 10 clocks per transaction. Physical implementation of pipelined AES with FPGA takes 3.5 times bigger gate counts than the non-pipelined version whereas the pipelined version yields only $3.5\%$ performance enhancement. The proposed analysis model can be used to optimize cost-performance of AES hardware designs.

• The Magazine of the IEIE
• /
• v.30 no.6
• /
• pp.584-593
• /
• 2003

시스템의 고속화와 정보통신망의 대용량화 추세에 적극 대응하기 위한 암호 알고리즘(대칭키, 공개키, 전자서명) 및 고속 암호 프로세서 등에 관한 국내외 표준 암호 기술 개발 동향을 살펴본다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2020.05a
• /
• pp.161-164
• /
• 2020

경량 암호는 컴퓨팅 파워가 부족한 저사양 프로세서를 위해 개발되었다. CHAM은 국산 경량 암호 중 하나로, 세 가지의 규격을 제공하며 ARX 구조를 사용한 암호이다. CHAM 발표 이후, 라운드 수를 조절하여 성능을 향상시킨 Revised CHAM이 제안되었다. 기존 CHAM은 8-bit AVR 프로세서 상에서 최적 구현이 이루어졌지만, 최신 기술인 Revised CHAM은 해당 구현물이 존재하지 않는다. 따라서 8-bit AVR 프로세서를 대상으로 Revised CHAM-64/128을 최적 구현하여 최상의 성능으로 연산이 진행되도록 한다. 본 논문에서는 최적 구현에 사용한 기법들을 소개하며, 기존에 제안된 기법과 성능 비교를 통해 본 기법의 우수함을 서술한다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.4
• /
• pp.795-803
• /
• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.852-855
• /
• 2005

This paper introduces a case study of designing a cryptographic processor dedicated to VPN/SSL system. The designed processor supports not only block cipher algorithm, including 3DES, AES, and SEED, but also 163 bit ECC public key crypto algorithm. Moreover, we adopted PCI Master interface in the design, which guarantees fast computation of cryptographic algorithm prevalent in general information security systems.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.31 no.3
• /
• pp.473-480
• /
• 2021

To achieve the high-speed implementation of post-quantum cryptography, primitive operations should be tailored to the architecture of the target processor. In this paper, we present the optimized implementation of multiplier operation on RISC-V processor for post-quantum cryptography. Particularly, the column-wise multiplication algorithm is optimized with the primitive instruction of RISC-V processor, which improved the performance of 256-bit and 512-bit multiplication by 19% and 8% than previous works, respectively. Lastly, we suggest the instruction extension for the high-speed multiplication on the RISC-V processor.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 2006.07a
• /
• pp.424-424
• /
• 2006