• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2754-2759
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• 2011

With information communications and RFID/USN environments merged wire/wireless networks are generalized. In this viewpoint, WAP is used by communication protocol for the data communication in the field of wireless environment. WTLS developed for the secure communications optimize TLS adapted wireless environment in the TCP/IP internet protocol. But WTLS denote WAP security problem, end-to-end problem, and power consumption, etc. Therefore in this paper we proposed WTLS cryptographic algorithm eliminated WTLS disadvantages. Proposed algorithm solved power consumption, calculated complexity, and security problems because it is not unique but hybrid form.

• Journal of the Korean Data and Information Science Society
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• v.20 no.1
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• pp.125-137
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• 2009

Smart card has a small sized micro computer chip. This chip contains processor, RAM, ROM, clock, bus system and crypto-co-processor. Hence it is more expensive, complicated and secure chip compared with RFID tag. The main application area of smart card is e-banking and secure communications. There are two kinds of smart card platforms; open platform and closed one. Java card is the most popular open platform because of its security, platform independency, fast developing cycle. However, the speed of Java card is slower than other ones, hence there have been hot research topics to improve the performance of Java card. In this paper, we propose an efficient transaction buffer management to improve the performance of Java card. The experimental result shows the advantage of our method.

• KIISE Transactions on Computing Practices
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• v.21 no.7
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• pp.476-481
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• 2015

We have parallelized the cumulative sum (CUSUM) test of NIST's statistical random number test suite in a CUDA environment. Storing random walks in an array instead of in scalar variables eliminates data dependence. The change in data structure makes it possible to apply parallel scans, scatters, and reductions at each stage of the test. In addition, serial data exchanges between CPU and GPU are removed by migrating CPU's tasks to GPU. Finally we have optimized global memory accesses. The overall speedup is 23 times over the sequential version. Our results contribute to improving security of random numbers for cryptographic keys as well as reducing the time for evaluation of randomness.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.1
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• pp.41-47
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• 2008

This paper presents a new digit level LSB-first multiplier for computing a modular multiplication and a modular squaring simultaneously over finite field GF($2^m$). To derive $L{\times}L$ digit level architecture when digit size is set to L, the previous algorithm is used and index transformation and merging the cell of the architecture are proposed. The proposed architecture can be utilized for the basic architecture for the crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity, and concurrency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.1
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• pp.11-19
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• 2024

The increased utilization of the FFT in signal processing, cryptography, and various other fields has highlighted the importance of optimization. In this paper, we propose the implementation of an accelerator that processes the radix-2 16 points FFT algorithm more rapidly and efficiently than FFT implementation of existing studies, using FPGA(Field Programmable Gate Array) hardware. Leveraging the hardware advantages of FPGA, such as parallel processing and pipelining, we design and implement the FFT logic in the PL (Programmable Logic) part using the Verilog language. We implement the FFT using only the Zynq processor in the PS (Processing System) part, and compare the computation times of the implementation in the PL and PS part. Additionally, we demonstrate the efficiency of our implementation in terms of computation time and resource usage, in comparison with related works.

• Journal of KIISE
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• v.44 no.5
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• pp.537-544
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• 2017

As a special form of the signed-digit representation, the NAF(non-adjacent form) minimizes the hamming weight by reducing the average density of the non-zero bits from the binary representation of the positive integer k. Due to this advantage, the NAF is used in various fields; in particular, it is actively used in cryptology. The existing NAF-conversion algorithm, however, is problematic because the conversion speed decreases when the LSB(least significant bit) frequently becomes "1" during the binary positive integer conversion process. This paper suggests a method for the improvement of the NAF-conversion speed for which the problems that occur in the existing NAF-conversion process are solved. To verify the performance improvement of the algorithm, the CPU cycle for the various inputs were measured on the ATmega128, a low-performance 8-bit microprocessor. The results of this study show that, compared with the existing algorithm, the suggested algorithm not only improved the processing speed of the major patterns by 20% or more on average, but it also reduced the NAF-conversion time by 13% or more.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.11
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• pp.581-588
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• 2007

In Digital Right Management, symmetric cipher is used for content encryption to reduce encryption cost, AES, advanced encryption standard is usually used to multimedia encryption under desktop environment because of its reasonable security level and computation cost. But mobile handheld device often uses slow speed processor and operates under battery-powered environment. Therefore it requires low computation cost and low energy consumption. This paper proposes new stream cipher scheme which combines pseudo random number generator(PRNG) and dynamically generated permutations. Proposed scheme activates PRNG and generates original key streams. Then it generates extended key streams by applying permutation to original sequence. These extended key streams are XORed with plaintext and generate ciphertext. Proposed scheme reduces the usage of PRNG. Therefore this scheme is fast and consumes less energy in comparison with normal stream cipher. Especially, this scheme shows great speed up (almost 2 times) than normal stream cipher scheme in random access.

• Journal of IKEEE
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• v.23 no.4
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• pp.1321-1327
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• 2019

This paper describes an efficient hardware implementation of modular square root (MSQR) computation over GF(p), which is the operation needed to map plaintext messages to points on elliptic curves for elliptic curve (EC)-ElGamal public-key encryption. Our method supports five sizes of elliptic curves over GF(p) defined by the National Institute of Standards and Technology (NIST) standard. For the Koblitz curves and the pseudorandom curves with 192-bit, 256-bit, 384-bit and 521-bit, the Euler's Criterion based on the characteristic of the modulo values was applied. For the elliptic curves with 224-bit, the Tonelli-Shanks algorithm was simplified and applied to compute MSQR. The proposed method was implemented using the finite field arithmetic circuit with 32-bit datapath and memory block of elliptic curve cryptography (ECC) processor, and its hardware operation was verified by implementing it on the Virtex-5 field programmable gate array (FPGA) device. When the implemented circuit operates with a 50 MHz clock, the computation of MSQR takes about 18 ms for 224-bit pseudorandom curves and about 4 ms for 256-bit Koblitz curves.

• Journal of the Korea Society of Computer and Information
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• v.25 no.2
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• pp.11-19
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• 2020

Modern GPU can execute general purpose computation on the graphic processing unit, and provide high performance by exploiting many core on GPU. To run AES algorithm efficiently, parallel computational resources are required. However, computational resource of CPU architecture are not enough to cryptographic algorithm such as AES whereas GPU architecture has mass parallel computation resources. Therefore, this paper reduce the time to execute AES by employing parallel computational resource on GPGPU. Unfortunately, AES cannot utilize computational resource on GPGPU since it isn't suitable to GPGPU architecture. In this paper, IPC based dynamic SM management technique are proposed to efficiently execute AES on GPGPU. IPC based dynamic SM management can increase and decrease the number of active SMs by using IPC in run-time. According to simulation results, proposed technique improve the performance by increasing resource utilization compared to baseline GPGPU architecture. The results show that AES improve the performance by 41.2% on average.

• Journal of the Korea Society of Computer and Information
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• v.13 no.5
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• pp.195-202
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• 2008

In this paper, To improve the effectiveness of security enforcement, the first contribution in this work is that we present a clustered heterogeneous WSN(Wareless Sensor Network) architecture, composed of not only resource constrained sensor nodes, but also a number of more powerful high-end devices acting as cluster heads. Compared to sensor nodes, a high-end cluster head has higher computation capability, larger storage, longer power supply, and longer radio transmission range, and it thus does not suffer from the resource scarceness problem as much as a sensor node does. A distinct feature of our heterogeneous architecture is that cluster heads are equipped with TC(trusted computing) technology, and in particular a TCG(Trusted Computing Group) compliant TPM (Trusted Platform Module) is embedded into each cluster head. According the TCG specifications, TPM is a tamper-resistant, self-contained secure coprocessor, capable of performing cryptographic functions. A TPM attached to a host establishes a trusted computing platform that provides sealed storage, and measures and reports the integrity state of the platform.