• Journal of KIISE:Computing Practices and Letters
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• v.16 no.12
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• pp.1177-1187
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• 2010

Flash memory becomes popular storage for small devices due to its efficiency, portability, low power consumption and large capacity. Unlike on hard disks, however, write operation on flash memory is much more expensive than read operation, so that it is critical for performance enhancement to reduce the number of executions of write operation. This paper proposes static analysis to rewrite a program to reduce the total number of write operations by merging writable data in a minimum number of pages. To achieve this, we collect information about writable areas by static analysis, and about frequently executed paths by profiling for practicality, and combine both to rewrite the application program to reallocate data. The performance enhancement gained from the proposed methods is shown using a FAST simulator.

• The KIPS Transactions:PartA
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• v.18A no.4
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• pp.135-142
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• 2011

This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.05a
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• pp.1333-1336
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• 2006

본 논문에서는 최근에 각광받고 있는 저장장치인 플래시 메모리의 특징과 플래시 메모리의 단점인 지움 횟수 제한과 느린 지움 속도를 극복하는 지움 정책의 종류를 살펴보고 그 중에서 CAT 기법의 랜덤 쓰기에서의 지움 횟수 증가와 지움 평준화를 위한 비효율성이라는 단점을 개선한 지움 정책을 제시한다. 개선된 지움 정책은 CAT 기법에 쓰기 패턴을 기반한 가중치를 부여해 랜덤 쓰기에서의 성능 하락과 지움 평준화의 비효율성을 보완하는 것이다. 이 때 사용되는 사용자의 쓰기 패턴 파악은 유효한(valid) 데이터 블록과 유효하지 않은(invalid) 데이터 블록의 리스트를 만들어 그 시간 값의 평균을 이용한다.

• Journal of Internet of Things and Convergence
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• v.8 no.4
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• pp.9-15
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• 2022

NAND flash memory is used as a medium for various storage devices due to its high data processing speed with low power consumption. However, since the read processing speed of data is about 10 times faster than the write processing speed, various studies are being conducted to improve the speed difference. In particular, flash dedicated buffer management policies have been studied to improve write speed. However, SSD(solid state disks), which has recently been used for various purposes, is more vulnerable to read performance than write performance. In this paper, we find out why read performance is slower than write performance in SSD composed of NAND flash memory and study buffer management policies to improve it. The buffer management policy proposed in this paper proposes a method of improving the speed of a flash-based storage device by analyzing the pattern of read data and applying a policy of pre-reading data to be requested in the future from NAND flash memory. It also proves the effectiveness of the read-ahead policy through simulation.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.93-96
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• 2013

모바일 환경에서 전력 손실이 중요한 문제 중 하나가 됨에 따라, MRAM과 플래시메모리와 같은 비 휘발성 메모리가 차세대 모바일 컴퓨터에 널리 사용될 것이다. 본 논문에서는 DRAM/MRAM 하이브리드 메인 메모리의 제한적인 쓰기 연산 성능을 고려한 효율적인 버퍼 캐시 기법을 연구했다. 제안한 기법은 MRAM 의 제한적인 쓰기 연산 성능을 고려하고 플래시 메모리 저장 장치의 삭제 연산 횟수를 최소화한다.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.107-110
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• 2017

According to researches, while the speed of processor and network in embedded devices is fast enough to meet user requirement, the IO speed is recognized as the main performance bottleneck. Meanwhile it is known that more than 70 percent of IOs are issued from SQLite database. Many researches related SQLite performance optimization is based on WAL mode because WAL mode optimized for write IO performance. In this paper, I propose to optimize SQLite with Atomic Write in the Rollback Journal Mode, which is mainly used in Android and Tizen. I have observed that Atomic Write have a significant write performance improvement(300%) by reducing write, file sync operation and memory usage improvement(80%). Additionally it can block JOJ(Journaling of Journal) and extend the life of the flash memory.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2849-2860
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• 1997

In this paper, we present efficient cache replacement policies for the software RAID file system. The performance of this policies is compared to two other policies previously proposed for conventional file systems and adapted for the software RAID file system. As in hardware RAID systems, we found small-writes to be the performance bottleneck in software RAID file systems. To tackle this small-write problem, we propose cache replacement policies. Using trace driven simulations we show that the proposed policies improve performance in the aspect of the average response time and the average system busy time.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06a
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• pp.364-366
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• 2012

스마트폰의 어플리케이션은 어플리케이션 생태계의 발전에 따라 그 수가 많아지고, 업데이트 또한 잦아졌다. 어플리케이션의 업데이트는 낸드 플래시 메모리에 이전 버전을 삭제하고, 새로운 버전의 어플리케이션에 대한 쓰기 명령을 내린다. 따라서 사용자는 낸드 플래시 메모리에서의 상대적으로 느린 쓰기 명령에 의해 스마트폰의 성능의 저하를 느끼고 낸드 플래시 메모리는 반복되는 지우기/쓰기 동작에 의해 수명이 단축된다. 본 논문에서는 업데이트 되는 스마트폰 어플리케이션 데이터가 이전 버전과 큰 차이가 없다는 것에 착안하여 데이터 중복제거를 통해 업데이트 성능을 향상시키고 낸드 플래시 메모리의 수명을 향상시키는 기법을 제안하고 있으며, 실험을 통해서 어플리케이션들에 대한 중복 제거율을 관찰하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2016.10a
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• pp.12-15
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• 2016

데이터베이스 시스템의 트랜잭션 로깅이나 파일 시스템의 저널링에서 데이터 저장시 입출력 동기화(Synchronous I/O)는 올바른 프로르램 동작에 필수적이다. 하지만 입출력 동기화로 인한 프로그램의 지연 혹은 기다림은 응용 프로그램 성능의 저하를 가져온다. 본 논문에서는 차세대 저장장치인 비휘발성 메모리를 사용하여 지속성을 보장하며 쓰기 연산의 응답성을 개선하는 사용자 수준의 스토리지 모듈을 제안하고 기존의 동기화된 쓰기 연산과 성능을 비교하였다. 특히 멀티코어 환경에서 동시에 들어오는 여러 입출력 쓰기 연산 요청에 대하여 효율적으로 처리하였다.