• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.301-306
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method, and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point, the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.50-56
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• 2000

The integrated circuit interconnection lines are experimented with patterned ground shields (PGS) at microwave frequencies. Measurement results demonstrate that the PGS can significantly reduce the power loss through the interconnect lines over wide frequency ranges as the PGS shields the lossy silicon substrate. The transmission line characteristics of the PGS interconnect lines are analyzed and identified that the PGS reduces the wave length of the interconnect line.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.86-89
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• 1994

This paper describes the fabrication and basic characteristics of a Si Hall device fabricated on a SOI(Si-on-insulator) structure. In which SOI structure was formed by SOB(Si-wafer direct bonding) technology and the insulator of the SOI structure was used as the dielectrical isolation layer of a Hall device. The Hall voltage and sensitivity of the implemented SDB SOI Hall devices showed good linearity with respectivity to the applied magnetic flux density and supple iud current. The product sensitivity of the SDB SOI Hall device was average 670 V/A$.$T and its value has been increased up to 3 times compared to that of bulk Si with buried layer of 10$\mu\textrm{m}$. Moreover, this device can be used at high-temperature, high-radiation and in corrosive environments.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.82-82
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• 2011

본 연구에서는 이온빔 스퍼터링 방법으로 증착한 Cr2O3, Ta2O5, HfO2 산화물박막의 구조적 특성변화를 관찰하였다. 금속박막에서 표면이 산화되는 문제를 해결하기위하여 산화물 박막을 증착시켰다. 이온빔 스퍼터링으로 박막 증착 시 산화물 타겟을 사용할 때 발생되는 전하의 영향을 상쇄하기 위하여 neutralizer를 사용하였다. 박막 증착 후 XRR (X-ray Reflectometer)을 이용하여 박막의 두께, 거칠기 및 밀도를 확인하였으며, AFM (Atomic Force MicroScope)을 통하여 증착한 박막표면 거칠기 측정을 하여 XRR로 얻은 데이터와 비교하여 살펴보았다. 또한 XPS (X-ray photoelectron spectroscopy)측정을 통해 제조된 박막의 화학적 결합상태를 확인하였다. 여러 가지 조건변화와 기판의 차이에 따라 제작된 산화물 박막 중 실리콘 기판을 사용하여 증착시킨 박막은 XRR측정시 반사율 곡선에서 자연 산화막에 의한 영향이 나타났다. 반면 glass나 sapphire에 증착시킨 산화물 박막은 실리콘기판에서 나타난 자연 산화막의 영향을 받지 않음을 확인하였다. 기판과 산화물 박막사이에 계면층에 나타나는 영향을 최소화시킴으로써 양질의 박막을 제작할 수 있을 것으로 기대된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.370-373
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• 1999

Si direct bonding (SDB) technology is very attractive for both Si-on-insulator(SOI) electric devices and MEMS applications because of its stress free structure and stability. This paper presents on- pre treatment conditions in Si wafer direct bonding, The paper resents on pre-bonding according to HF pre-treatment conditions in Si wafer direct bonding. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, applied pressure and annealing temperature(200~ 100$0^{\circ}C$) after pre-bonding. The bonding strength was evaluated by tensile strength method. The bonded interface and the void were analyzed by using SEM and IR camera, respectively, Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding(Min 2.4kgf/$\textrm{cm}^2$~ Max : 14.kgf/$\textrm{cm}^2$)

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.583-586
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• 2000

The non-selective method by polishing after grinding was used widely to thinning of SDB SOI structures. This method was very difficult to thickness control of thin film, and it was dependent on equipments. However electrochemical etch-stop, one of the selective methods, was able to accurately thickness control and etch equipment was very simple. Therefore, this paper described with the effect of leakage current and electrodes on electrochemical etch-stop. Consequentially, PP(passivation potential) was changed according to the kinds of contact and contact sizes, but OCP(open current potential) was not change with range of -1.5~-1.3V

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.579-582
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• 2000

This paper described on the fabrication of SOI(Si-on-insulator) structures with buried cavities by SDB technology and eletrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annaling(100$0^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated the SDB SOI structure with buried cavities as well as an accurate control and a good flatness.

• Proceedings of the Korea Contents Association Conference
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• 2008.05a
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• pp.595-597
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• 2008

Zinc Oxide(ZnO) thin films on Si (100) substrate were deposited by RF magnetron sputter with changing sputtering conditions such as argon/oxygen gas ratios, RF power, and substrate temperature, chamber pressure and target-substrate distance. To analyze a crystallographic properties of the films, ${\Theta}/2{\Theta}$ mode X-ray diffraction, SEM analyses. C-axis preferred orientation highly depended on RF power.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.5
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• pp.431-436
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM respectively.

• Proceedings of the KAIS Fall Conference
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• 2001.11a
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• pp.169-172
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• 2001

다층 MEMS구조의 기초기판쌍 소재로 쓰일 수 있는 Si∥SiO₂/Si₃N₄∥Si 기판쌍의 직접접합 가능성을 확인하기 위해서 2000Å-SiO₂와 500Å-Si₃N₄층을 가진 직경 10cm의 실리콘 기판을 각각 친수성 및 소수성 표면세척을 하고 청정분위기에서 경면끼리 가접을 실시하였다. 가접된 기판쌍을 통상의 박스형 전기로를 이용하여 400, 600, 800, 1000, 1200℃ 범위에서 2시간 동안 가열하여 접합을 완료하였다. 완성된 기판쌍을 적외선분석기를 이용하여 접합면적을 확인하였고, 면도칼 삽입법으로 접합계면에너지를 측정하였다. 실험온도 범위 내에서 Si∥SiO₂/Si₃N₄∥Si 기판쌍은 1000℃ 이상에서 접합계면에너지는 2,344mJ/㎡을 나타냈으며, 이는 기존의 Si/Si의 동종접합기판쌍과 동등한 수준의 접합강도로서 부가가치가 큰 새로운 조합의 기판쌍 제조가 가능하였다.