• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.05a
• /
• pp.684-685
• /
• 2017

FMCW radar, which is widely used as a front collision warning system for vehicles, is now being commercialized. In this study we develope the radar signal processing system using MPC5775K that is specialized for high performance ADAS. That has special features for ADAS such as 10Msps 12bit ADC, 50MHz Radix-4 FFT, CTE(Cross Triggering Engine) for synchronized triggering between DAC and ADC. The baseband processing board is implemented and shows the result in Matlab.

• Journal of Astronomy and Space Sciences
• /
• v.13 no.2
• /
• pp.163-172
• /
• 1996

The objective of this paper is to show how digital signal processing experiment(DSPE) was designed and to present its experimental results in orbit and on the ground. The multi-missional and flexible DSPE was designed in a reliable manner. Among several experiments executed in orbit and on the ground, a high-speed(19.2kbps) software modulator experiment was discussed in this paper. A 32bit floating-type TMS320C30, which was developed for commercial purposes, was used on LEO micro-satellites, KITSAT-1 and KITSAT-2. This digital signal processor(DSP) can be applied to the various payloads of the next generation satellites.

• Journal of KIISE:Computing Practices and Letters
• /
• v.13 no.5
• /
• pp.252-259
• /
• 2007

With the rapid development of multimedia applications and wireless communication networks, consumer demand for video-over-wireless capability on mobile computing systems is growing rapidly. In this regard, this paper introduces YUV-aware instructions that enhance the performance and efficiency in the processing of color image and video. Traditional multimedia extensions (e.g., MMX, SSE, VIS, and AltiVec) depend solely on generic subword parallelism whereas the proposed YUV-aware instructions support parallel operations on two-packed 16-bit YUV (6-bit Y, 5-bits U, V) values in a 32-bit datapath architecture, providing greater concurrency and efficiency for color image and video processing. Moreover, the ability to reduce data format size reduces system cost. Experiment results on a representative dynamically scheduled embedded superscalar processor show that YUV-aware instructions achieve an average speedup of 3.9x over the baseline superscalar performance. This is in contrast to MMX (a representative Intel#s multimedia extension), which achieves a speedup of only 2.1x over the same baseline superscalar processor. In addition, YUV-aware instructions outperform MMX instructions in energy reduction (75.8% reduction with YUV-aware instructions, but only 54.8% reduction with MMX instructions over the baseline).

• Journal of the Korea Institute of Military Science and Technology
• /
• v.4 no.2
• /
• pp.179-188
• /
• 2001

The objective of this paper is to design and implement sliding mode control scheme for an actuation system using BLDC motor. Since the dynamic characteristics of this system with unknown disturbance and parameter variations are very complicated and highly nonlinear, the conventional linear control approaches may not guarantee satisfactory control performances. In order to improve the dynamic performances of this system, a model following sliding mode control(MFSMC) with perturbation estimation approach is designed and implemented. It eliminates the conventional requirements for the knowledge of uncertainty upper boundary. The effectiveness of this control approach is verified by comparison with a PID control through a series of simulation and experimental studies.

• Journal of the Korean Society for Nondestructive Testing
• /
• v.26 no.2
• /
• pp.99-107
• /
• 2006

Magnetic nondestructive testing is very useful far detecting a crack on the surface or near of the surface of the ferromagnetic materials. The distribution of the magnetic flux leakage (DMFL) on a specimen has to be obtained quantitatively to evaluate the crack. The magnetic camera is proposed to obtain the DMFL at the large lift-off. The magnetic camera consists of a magnetic source, magnetic lens, analog to digital converters (ADCs), interface, and computer. The magnetic leakage fields or the distorted magnetic fields from the object, which are concentrated on the magnetic lens, are converted to analog electrical signals tv arrayed small magnetic sensors. These analog signals are converted to digital signals by the ADCs, and are stored, imaged, and processed by the interface and computer. However the magnetic camera has limitations with respect to converting and switching speed, full range and resolution, direct memory access (DMA), temporary storage speed and volume because common ADCs were used. Improved techniques, such as those that introduce the operational amplifier (OP-Amp), amplify the signal, reduce the connection line, and use the low pass filter (LPF) to increase the signal to noise ratio are necessary. This paper proposes the exclusive embedded ADC including OP-Amp, LPF, microprocessor and DMA circuit for the magnetic camera to satisfy the conditions mentioned above.

• The Journal of Information Technology
• /
• v.4 no.4
• /
• pp.51-63
• /
• 2001

Residue Number System has carry free operation and parallelism each modulus, So it is used for special purpose processor such as Digital Signal Processing and Neuron Processor. Magnitude comparison and sign detection are in need of Mixed Radix Conversion, and these operations are impediment to improve the operation speed. So in this Paper, MRC(Mixed Radix Converter) is designed using modified partitioned residue to speed up the operation of MRC, so it has progressed maximum twice operation time but increased the size of converter comparison to other converter.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.2
• /
• pp.1-13
• /
• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.228-231
• /
• 1999

This paper describes the design and implementation of an application specific instruction-set processor developed for embedded DSP applications. The instruction-set has an uniform size of 16 bits, and supports 3 types of instructions: Primitive, Complex, and Specific. To reduce code size and cycle count we introduce complex instructions that can be selected according to the application under consideration, which leads to 50% code size reduction maximally. The processor has two independent data memories to double the data throughput and the address space. The processor is synthesized by 0.6$\mu$m single-poly double-metal technology. Critical path simulation shows that the maximum frequency is 110MHz and total gate count is 132, 000.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.44 no.5
• /
• pp.12-19
• /
• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.11
• /
• pp.53-61
• /
• 2002

This paper proposes new DSP instructions and their architecture which efficiently implements the Viterbi decoding algorithm. The proposed architecture, supporting typical signal processing functions as in existing DSP chips, consists of an array of operational units and data path structures adequate to the Viterbi algorithm. While existing DSP chips perform Viterbi decoding at the rate of about several dozen kbps, the proposed architecutre can give the rate of 6.25 Mbps on 100 MHz DSP chips, which is nearly the same performance as that of custom-designed Viterbi processors. Therefore, the architecture can meet the standard of IMT-2000 having the 2Mbps data rate.