• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2628-2635
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• 2010

This paper analyzes the detection probability of FMCW (Frequency Modulated Continuous Wave) radar based on Doppler frequency and analog-digital converter bit and designs and implements signal processing part of FMCW radar. For performance evaluation, the FMCW radar system consists of a transmitted part and a received part and uses AWGN channel. The system model is verified through analysis and simulation. Frequency offset occurs in the received part caused by the mismatching between the received signal and the reference signal. In case of Doppler frequency less than about 38KHz, performance degradation of detection does not occur in FMCW radar with 75cm resolution The analog-digital converter needs at least 6 bit in order not to degrade the detection probability. And, we design and implement digital signal processing part based on DDS chip of digital transmitted signal generator for FMCW radar.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.37-39
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• 2002

컴퓨터의 보급과 통신의 발달에 따라 많은 자료가 모뎀 등의 장비를 통하여 네트워크 상에서 이동하고, 인간의 음성, 혹은 소리가 컴퓨터에 사용되게 되었다. 이에 따라 소리, 네트워크 상의 자료와 같은 아날로그 신호와 컴퓨터가 처리할 수 있는 디지털 신호간의 변환이 필요하게 되었다. 본 연구에서는 CCITT에서 제안한 아날로그, 디지털 변환 알고리즘인 ADPCM 알고리즘, G.721, G.726에 따라 아날로그, 디지털 변환기를 하드웨어 기술언어인 VHDL을 사용하여 실제적으로 구현하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.101-104
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• 2001

In this paper, we propose the Digital Automatic Gain Controller for IEEE 802.11a High-speed Physical Layer in the 5 GHz Band. The input gain is estimated by calculating the energy of the training symbol that is a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.6
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• pp.1402-1409
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• 2007

In this paper, we propose various types of AGC algorithms for implementing the OFDM communication systems. For the high-speed packet transmission, in this paper, we assume the OFDM system with relatively long and repeated preambles. We propose the maximum sample value counter for counting the number of maximum sample. In the maximum sample value counter, we use the buffer for the digital signal buffering. Finally, the counting value of the maximum sample value counter controls the gain control signal generator by using gain control table automatically.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.8
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• pp.678-688
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• 1990

In this paper, pSDF-based referance image is realized. Using BJTC(binary joint transform correlator) as the spatial plane correlator, optical pattern recognition for intraclass indentification is performed. Computer simulation shows that the correlation performance of BJTC is superior to that of JTC. Experimental results using BJTC reveal that correlation peak intensity is constant within the error range from 4.1% to 9.6% in intraclass indentification.

• Proceedings of the Optical Society of Korea Conference
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• 2001.02a
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• pp.36-37
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• 2001

광통신 시스템이 널리 사용되기 시작한 이래 광섬유를 통한 원거리 전송에 따른 신호의 감쇠와 왜곡 등의 문제점이 발생하게 되고 이를 보상하기 위해 중계기(Repeater)의 사용이 요구된다. 이러한 중계기에는 광전변환, 전기신호처리 및 전광변환 등의 번거러움이 따른다. 이와 같은 번거로움 때문에 광통신 시스템 설계자들은 광전, 전광 변환 없이 바로 광신호 자체의 세기를 증폭하는 기술을 필요로 하게 되었다. 특히 최근 들어 파장분할다중(Wavelength Division Multiplexing)광 네트웍 및 광통신의 고속화가 요구됨에 따라 중계기를 광증폭기로 대치하는 추세는 더욱 가속화되고 있다. (중략)

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.119-120
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• 2004

Split-beam 트랜스듀서의 입력신호로써 Sweep 신호를 구동한 어군탐지기 SONAR에 대하여 기술한다. Sweep 신호의 대역폭은 트랜스듀서 공진 대역의 대역폭에서 주파수 이동 변환하였다. 목표 대상물의 방위각 추정은 각 수신 채널 사이의 크로스-스펙트럼을 사용하여 추정한다. 추정 방위각의 정확도는 제안한 시스템의 알고리듬에 관계하고 있다.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2001.05a
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• pp.217-223
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• 2001

본 논문에서는 기존의 AV용 적외선 송수신 시스템을 중간 매체로 이용하고, 그의 대역내에서 디지털 비트스트림을 고속으로 송수신할 수 있는 적외선 무선 데이터 통신 시스템을 제안 및 구현하였다. 제안한 시스템의 송신측에서는 디지털 비트스트림을 NTSC 비디오 신호 규격과 유사한 형태의 아날로그 신호로 변환하고, 이를 기존의 적외선 송신기로 무선 전송한다. 수신측에서는 기존의 적외선 수신기로 아날로그 신호를 수신하고, 이를 다시 디지털 비트스트림으로 변환한다. 본 논문의 결과는 다양한 AV시스템에서 적외선을 이용한 고속 무선 데이터 송수신에 응용될 수 있을 것이다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.1
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• pp.364-370
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• 2011

The Hilbert transform performs a role to transform band pass signals into low pass signals in wireless communication systems. The operation of Hilbert transform is based on a convolution process which is required adding and multiplying calculations. When the Hilbert transform is designed and hardware-implemented at gate level, the adding and multiplying operation requires a high power consumption and a occupation of wide area on a chip. So the results of adding and multiplying operation cause to degrade the performance of implemented system. In this paper, the new Hilbert transformer is proposed, which has a low hardware complexity by application of MAG(Minimum Adder Graph) algorithm. The proposed Hilbert transformer was simulated in ISE environment of Xilinx and showed the reduction of hardware complexity comparing with the number of gate in the conventional Hilbert transformer.