• Title/Summary/Keyword: 신호변환기

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Implementation of Wideband Low Noise Down-Converter for Ku-Band Digital Satellite Broadcasting (Ku-대역 광대역 디지탈 위성방송용 저 잡음하향변환기 개발)

  • Hong, Do-Hyeong;Lee, Kyung Bo;Rhee, Young-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.2
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    • pp.115-122
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    • 2016
  • In this paper, wideband Ku-band downconverter was designed to receiver digital satellite broadcasting. The low-nose downconverter was designed to form four local oscillator frequencies(9.75, 10, 10.75 and 11.3 GHz) representing a low phase noise due to VCO-PLL with respect to input signals of 10.7 to 12.75 GHz and 3-stage low noise amplifier circuit by broadband noise matching, and to select intermediate frequency bands by digital control. The developed low-noise downconverter exhibited the full conversion gain of 64 dB, and the noise figure of low-noise amplifier was 0.7 dB, the P1dB of output signal 15 dBm, and the phase noise -85 dBc@10kHz at the band 1 carrier frequency of 9.75 GHz. The low noise block downconverter(LNB) for wideband digital satellite broadcasting designed in this paper can be used for global satellite broadcasting LNB.

Design of Low-power Serial-to-Parallel and Parallel-to-Serial Converter using Current-cut method (전류 컷 기법을 적용한 저전력형 직병렬/병직렬 변환기 설계)

  • Park, Yong-Woon;Hwang, Sung-Ho;Cha, Jae-Sang;Yang, Chung-Mo;Kim, Sung-Kweon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.10A
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    • pp.776-783
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    • 2009
  • Current-cut circuit is an effective method to obtain low power consumption in wireless communication systems as high speed OFDM. For the operation of current-mode FFT LSI with analog signal processing essentially requires current-mode serial-to-parallel/parallel-to-serial converter with multi input and output structure. However, the Hold-mode operation of current-mode serial-to-parallel/parallel-to-serial converter has unnecessary power consumption. We propose a novel current-mode serial-to-parallel/parallel-to-serial converter with current-cut circuit and full chip simulation results agree with experimental data of low power consumption. The proposed current-mode serial-to-parallel/parallel-to-serial converter promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

Study on Performance Improvement and Size Reduction Using Active Inductors in MMIC Frequency Converter (능동인덕터 사용에 따른 MMIC 주파수 변환기의 성능향상과 면적축소에 관한 연구)

  • 구현철;박정호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.7
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    • pp.1296-1303
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    • 1994
  • In this paper, a design of active inductors and their application in a frequency converter are proposed. In MMIC design, passive spiral inductor takes larger area than any other passive and active elements. A conventional spiral inductor generates undesired crosstalk, and its performance cannot have certainty and reproducibility. Meanwhile the active inductor eliminates these drawbacks, and operates for much wider bandwidth. Furthermore, its size is smaller and nearly independent of inductance. the performance of MMIC frequency converter with active inductors is directly compared with that of the frequency converters with spiral inductors. The size is 28.6% smaller with better performance in MMIC frequency converter.

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A 10-bit 10-MS/s 0.18-㎛ CMOS Asynchronous SAR ADC with split-capacitor based differential DAC (분할-커패시터 기반의 차동 디지털-아날로그 변환기를 가진 10-bit 10-MS/s 0.18-㎛ CMOS 비동기 축차근사형 아날로그-디지털 변환기)

  • Jeong, Yeon-Ho;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.2
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    • pp.414-422
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    • 2013
  • This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

The Fast Correlative Vector Direction Finder Conversion (직접 변환을 이용한 고속 상관형 벡터 방향탐지기)

  • Park, Cheol-Sun;Kim, Dae-Young
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.12 s.354
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    • pp.16-23
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    • 2006
  • This paper presents the development of the fast Direction Finder using direct conversion method, which can intercept for short pulse signal of less' than 1 msec. in RF Down Converter, and CVDF(Correlative Vector Direction Finding) algorithm, which estimates DoA (Direction of Arrival). The configuration and characteristics of direction finder using 5-channel equi-spaced circular array antenna are presented and the direct conversion techniques for removing tuning time using I/Q demodulator are described. The CRLB of our model is derived, the principles of 2 kind of CVDF algorithm are explained and their characteristics are compared with CRLB w.r.t the number of samples and spacing ratio. The RF Down Converter prototype using direct conversion method is manufactured, the 2 kind of CVDF algorithm are applied and their performance are analyzed. Finally it is confirmed the LSE based CVDF algorithm is better than correlation-coefficient based except for ambiguity protection capabilities.

An Implementation of Digital IF Receiver for SDR System (SDR(Software Defined Radio)시스템을 위한 디지털 IF수신기 구현)

  • 송형훈;강환민;김신원;조성호
    • Proceedings of the IEEK Conference
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    • 2001.09a
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    • pp.951-954
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    • 2001
  • 본 논문에서는 SDR (Software Defined Radio)시스템을 위한 디지털 IF (Intermediate Frequency)수신기를 구현하였다[1][2]. 구현된 수신기의 하드웨어 구조는 AD변환부, PDC(Programmable Down Converter)부, DSP (Digital Signal Processing)부분으로 이루어졌다. AD변환부는 Analog Devices사의 AD6644를 이용하여 아날로그 신호를14bit의 디지털 신호로 변환된다. PDC부분은 Intersil사의 HSP 50214B를 이용하여 14bit 샘플 된 IF(Intermediate Frequency)입력을 혼합기와 NCO(Numerically Controlled Oscillator)에 의해 기저대역으로 다운 시키는 역할을 한다. PDC는 CIC (Cascaded Integrator Comb)필터, Halfband 필터 그리고 프로그램할 수 있는 FIR필터로 구성되어 있다. 그리고 PDC부분을 제어하고 PDC부분에서 처리할 수 없는 캐리어, 심볼 트래킹을 위해 Texas Instrument사의 16비트의 고정소수점 DSP인 TMS320C5416과 Altera사의 FPGA를 사용하였다. 그러므로 중간주파수 대역과 기저대역 간의 신호변환을 디지털 신호처리를 수행함으로써 일반적인 아날로그 처리방식보다 고도의 유연성과 고성능 동작이 가능하고 시간과 환경 변화에 우수한 동작 특성을 제공한다.

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Digital IF Designs for SDR in Simulink (Simulink에서의 SDR을 위한 Digital IF 설계)

  • Woo, Choon-Sic;Kim, Jae-Yoon;Lee, Chang-Soo;Yoo, Kyung-Yul
    • Proceedings of the KIEE Conference
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    • 2002.07d
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    • pp.2589-2591
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    • 2002
  • 송수신기의 방식에는 직접변환 방식과 기저대역 신호와 LO(Local Oscillator)를 혼합하여 interpolation 기법을 사용하여 중간 주파수 단계까지 up conversion을 하고 두 번째 LO와 IF신호를 혼합하여 RF신호로 변환하여 송신하는 헤테로다인 방식이 존재한다. 본 논문에서는 이런 송수신기 방식 중에서 헤테로다인 방식을 적용하여 QPSK에서의 digital up /down converter를 Simulink 환경에서 설계 및 구현하였다. Up converter는 4배의 interpolation 필터와 4단짜리 cascaded integrate-comb(CIC)필터를 사용하여 입력데이터의 샘플 레이트를 클럭 레이트까지 증가시켰으며, numerically controlled oscillator (NCO)와 mixer를 사용하여 신호를 변조하였다. Down converter의 구조는 up converter와 동일하며 단지 up converter의 반대순서로 구성되어있다. 이런 모든 과정을 Simulink를 이용한 시뮬레이션과 스펙트럼 분석기를 사용하여 검증해 보았다.

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Study on the Broadband RF Front-End Architecture (광대역 RF 전단부 구조에 관한 연구)

  • Go, Min-Ho;Pyo, Seung-Chul;Park, Hyo-Dal
    • The Journal of the Korea institute of electronic communication sciences
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    • v.4 no.3
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    • pp.183-189
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    • 2009
  • In this paper, we propose RF front-end architecture using hybrid conversion method to receive broadband signal. The validity is verified by design, fabrication and experiment. The proposed RF front-end architecture due to up-conversion block improves the deficiency of performance deterioration to be generated through harmonic signal and image signal conversion in the conventional RF front-end, and improves the deficiency of the complexity that is from to adopt a multiple local oscillators for the generation of wideband LO signal in the conventional RF front-end by applying the principle that tuning bandwidth is multiplied at sub-harmonic mixer. Manufactured circuits satisfy the deduced design specification and target standard with gain above 80 dB, noise figure below 6.0 dB and IIP3 performance above -5.0 dBm for the condition of the minimum gain in RF front-end.

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An Implementation of a GPS Signal Generator based on FPGA and Indoor Positioning System (FPGA를 기반으로 한 GPS 신호생성기 구현 및 실내측위 시스템)

  • Choi, Jun-hyeok;Kim, Young-Geun;Ahn, Myung-Soo
    • Journal of Satellite, Information and Communications
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    • v.10 no.3
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    • pp.38-43
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    • 2015
  • This paper describes a GPS signal generator that can generate multiple satellite signals in real time at the RF level. It realizes the verified software algorithm on a FPGA. The algorithm models orbits and environmental errors such as ionospheric and tropospheric multipath. The position of a simulated receiver is one of simulation parameters. The hardware which consists of a digital logic board and an analog board can generate 16 simulated satellites signals at the same time. The users can generate spoofing signals and jamming signals as well as satellite signals by using the windows-based control software. In addition, the software provides GIS-based simulation scenarios editing tools. We verified the generator by using commercial receivers. As an application, we configured generators as indoor positioning systems and tested them in a building. To improve the accuracy of indoor systems is our further study.

Design for OAM Translator in Heterogeneous Networks (이종망간 OAM 상호 연동을 위한 변환기 설계)

  • 양진홍;강수진;김철수
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.04a
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    • pp.715-717
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    • 2004
  • 인터넷의 폭발적인 성장으로 인하여 MAN(Metropolitan Area Network)은 기존 음성 트래픽 전송 중심의 SONET/SDH(Synchronous Optical NETwork/Synchronous Digital Hierarchy) 환경에서 데이터 트래픽을 수용 할 수 있는 MSPP(MultiService Provisioning Platform) 환경으로 변해가고 있다. 이러한 네트워크 환경에서 이종 망간의 스위칭 역할을 수행하는 NG-SDH장비는 각 망간의 OAM을 제공하기 위해 OAM(Operation/Administration/Maintenance)신호에 대한 IWF(InterWorking Function) 기능을 필요로 하게 된다. 본 논문은 이종 망간 OAM 기능 제공을 위한 IWF에 대해 분석, 정의하고 이를 기반으로 NG-SDH 장비 블록 내에서 이종망간 OAM 기능을 제공할 OAM 변환기를 설계하였다.

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