• Journal of KIISE:Databases
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• v.37 no.6
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• pp.308-314
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• 2010

As the price of flash memory continues to drop and the technology of flash SSD controller innovates, high performance flash SSDs with affordable prices flourish in the storage market. Nevertheless, it is hard to expect that flash SSDs will replace harddisks completely as database storage. Instead, the approach to use flash SSD as a cache for harddisks would be more practical, and, in fact, several hybrid storage architectures for flash memory and harddisk have been suggested in the literature. In this paper, we propose a new approach to use flash SSD as an extended buffer for main buffer in database systems, which stores the pages replaced out from main buffer and returns the pages which are re-referenced in the upper buffer layer, improving the system performance drastically. In contrast to the existing approaches to use flash SSD as a cache in the lower storage layer, our approach, which uses flash SSD as an extended buffer in the upper host, can provide fast random read speed for the warm pages which are being replaced out from the limited main buffer. In fact, for all the pages which are missing from the main buffer in a real TPC-C trace, the hit ratio in the extended buffer could be more than 60%, and this supports our conjecture that our simple extended buffer approach could be very effective as a cache. In terms of performance/price, our extended buffer architecture outperforms two other alternative approaches with the same cost, 1) large main buffer and 2) more harddisks.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.7
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• pp.334-341
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• 2016

In this paper, the study of a waveguide aperture-coupled feed-structured antenna has been conducted for the purpose of applying it to a wireless back-haul system sufficient for high-capacity gigabits-per-second data rates. For this study, a $32{\times}32$ waveguide slot sub-array antenna with a corporate-feed structure was designed and produced. Also, this antenna is used at 57 GHz to 66 GHz in the V-band. The construction of the antenna is a laminated form with radiating parts (outer groove and slot, cavity), a coupled aperture, and feeds in each. The antenna was designed with HFSS, which is based on 3D-FEM, produced with aluminum processed by a precision-controlled milling machine, and assembled after a silver-plating process. The measurement result from analysis of the characteristics of the antenna shows that return loss is less than -12 dB, VSWR < 2.0, and a wide bandwidth ranges up to 16%. An overall first side lobe level is less than -12.3 dB, and a 3 dB beam width is narrow at about $1.85^{\circ}$. Also, antenna gain is 38.5 dBi, offering high efficiency exceeding 90%.

• KIPS Transactions on Software and Data Engineering
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• v.1 no.3
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• pp.159-168
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• 2012

Relation in the new IT environment, such as the SNS, Cloud, Web3.0, has become an important factor. And these relations generate a transaction. However, existing relational database and graph database does not processe graph structure representing the relationships and transactions. This paper, we propose the technique that can be processed concurrently graph structures and transactions in a scalable complex network system. The proposed technique simultaneously save and navigate graph structures and transactions using the Topic Maps data model. Topic Maps is one of ontology language to implement the semantic web(Web 3.0). It has been used as the navigator of the information through the association of the information resources. In this paper, the architecture of the proposed technique was implemented and design using Cassandra - one of column type NoSQL. It is to ensure that can handle up to Big Data-level data using distributed processing. Finally, the experiments showed about the process of storage and query about typical RDBMS Oracle and the proposed technique to the same data source and the same questions. It can show that is expressed by the relationship without the 'join' enough alternative to the role of the RDBMS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.36-44
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• 2007

This paper presented a hybrid ternary encoding scheme using 3-valued logic. It can adapt to the delay-insensitive(DI) model. We designed an asynchronous wrapper for the hybrid ternary encoding scheme to communicate with various asynchronous encoding schemes. It reduced about 50% of transmission lines and power consumption compared with the conventional 1-of-4 and ternary encoding scheme. The proposed wrappers were designed and simulated using the $0.18-{\mu}m$ standard CMOS technology. As a result, the asynchronous wrapper operated over 2 GHz communicating with a system bus. Moreover, the power dissipation of the system bus adapted the hybrid ternary encoding logic decreases 65%, 43%, and 36% of the dual-rail, 1-of-4, and ternary encoding scheme, respectively. The proposed data encoding scheme and the wrapper circuit can be useful for asynchronous high-speed and low-power asynchronous interface.

• Convergence Security Journal
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• v.19 no.4
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• pp.23-34
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• 2019

This study utilized big data, one of the new technologies of the Fourth Industrial Revolution as a policy direction study related to the military security of the Army. By utilizing Text mining and analyzing military security trends in domestic and foreign papers, it will be able to set policy directions and reduce trial and error. In this study, we found differences in domestic and international studies on military sucurity. At first, Domestic research has shown that in the course of the fourth industrial revolution, there is a strong interest in technological security, such as IT technology in security and cyber security in North Korea. On the other hand, Foreign research confirmed that policies are being studied in such a way that military sucurity is needed at the level of cooperation between countries and that it can contribute to world peace. Various academic policy studies have been underway in terms of determining world peace and security levels, not just security levels. It contrasted in our immediate confrontation with North Korea for decades but suggest complementary measures that cannot be overlooked from a grand perspective. Conclusionally, the direction of academic research in domestic and foreign should be done in macro perspective under national network cooperation, not just technology sucurity research, recognizing that military security is a policy product that should be studied in a security system between countries.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.327-332
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• 2002

Conventional proxy web cache, which is generally used to caching server, is a content-copy based system. This method focuses on speeding up the phase delivery not improving the webserver performance. However, if immense clients attempt to connect the webserver simultaneously, the proxy web cache cannot achieve the desired result. In this paper, we propose the web accelerator called the SCALA-AX, whitch improves web server performance by accelerating the delivery contents. The SCALA-AX is built in the Linux-based kernel as a kernel modulo and works in combination with the conventional webserver program. The SCALA-AX speeds up the processing rate of the webserver, because it processes the requests using the kernel thread. The SCALA-AX also applies the well-developed cache algorithm to the processing, and thus it obtains the advantage of the caching server without installing additional hardware. A banchmarking test demonstrates that the SCALA-AX improves webserver performance by up to 500％ for content delivery.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.8-15
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• 2009

Side-channel attacks including the differential power analysis attack are often more powerful than classical cryptanalysis and have to be seriously considered by cryptographic algorithm's implementers. Various countermeasures have been proposed against such attacks. In this paper, we deal with the masking method, which is known to be a very effective countermeasure against the differential power analysis attack and propose new gate-level conversion methods between Boolean and arithmetic masks. The new methods require only 6n-5 XOR and 2n-2 AND gates with 3n-2 gate delay for converting n-bit masks. The basic idea of the proposed methods is that the carry and the sum bits in the ripple adder are manipulated in a way that the adversary cannot detect the relation between these bits and the original raw data. Since the proposed methods use only bitwise operations, they are especially useful for DPA-securely implementing cryptographic algorithms in hardware which use both Boolean and arithmetic operations. For example, we applied them to securely implement the block encryption algorithm SEED in hardware and present its detailed implementation result.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.109-117
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• 2014

In navigation route planning systems using A* algorithms, the cardinality of an Open list, which is a list of candidate nodes through which a terminal node can be accessed, increases as the path length increases. In this paper, a method of alternately utilizing the Dijkstra's algorithm and the A* algorithm to reduce the cardinality of the Open list is investigated. In particular, by employing a depth parameter, named Level, the two algorithms are alternately performed depending on the Level's value. Using the hybrid searching approach, the Open list constructed in the Dijkstra's algorithm is transferred into the Open list of the A* algorithm, and consequently, the unconstricted increase of the cardinality of the Open list of the former algorithm can be avoided and controlled appropriately. In addition, an optimal or nearly optimal path similar to the Dijkstra's route, but not available in the A* algorithm, can be found. The experimental results, obtained with synthetic and real-life benchmark data, demonstrate that the computational cost, measured with the number of nodes to be compared, was remarkably reduced compared to the traditional searching algorithms, while maintaining the similar distance to those of the latter algorithms. Here, the values of Level were empirically selected. Thus, a study on finding the optimal Level values, while taking into consideration the actual road conditions remains open.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.41-49
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• 2010

This paper proposes a new high speed SHA-1 architecture using multiple unfolding and pre-computation techniques. We unfolds iterative hash operations to 2 continuos hash stage and reschedules computation timing. Then, the part of critical path is computed at the previous hash operation round and the rest is performed in the present round. These techniques reduce 3 additions to 2 additions on the critical path. It makes the maximum clock frequency of 118 MHz which provides throughput rate of 5.9 Gbps. The proposed architecture shows 26% higher throughput with a 32% smaller hardware size compared to other counterparts. This paper also introduces a analytical model of multiple SHA-1 architecture at the system level that maps a large input data on SHA-1 block in parallel. The model gives us the required number of SHA-1 blocks for a large multimedia data processing that it helps to make decision hardware configuration. The hs fospeed SHA-1 is useful to generate a condensed message and may strengthen the security of mobile communication and internet service.