• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.1
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• pp.76-80
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• 2010

It is floating to security of information and the early assignment that it is important it processes and to transmit in inundations of information that I changed suddenly. I used the encryption/decryption process that applied simple substitution and mathematical calculation algorithm at theory and encryption transmission steps protective early information. Hardware and financial loss are using spurious random number to be satisfied with the random number anger that isn't real random number to size so much perfect information protection using One-time pad for applying this. I was transformed into serial test under a test to prove spurious random number anger, and it is into random number anger stronger, and the transformation serial test that proposes is proving it in algorithm speed and efficiency planes.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.143-154
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• 2002

Recently, new appliances have become built-in ethernet Port but most of the old devices have serial port. So, it complicates and needs long time to maintain at a long distance. It can only controllable and fixable using modem. In this paper, we developed an embedded STEP converter within Linux operating system and other application software so that serial devices(PBX) can control in the ethernet network After completion of development processes, test was conducted. In the remote places, it was connected the STEP converter and controled the serial PBX. Finally, we confirmed that it can apply to other equipments.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.343-345
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• 2003

본 논문은 windows 상에서 디바이스 드라이버 구현을 위하여 타겟 디바이스를 사용하기 이전에 가상의 범용 디바이스 드라이버 개발도구를 이용하여 시뮬레이션 함으로써 최종 타겟 디바이스 개발의 효율성을 증대하고 개발 기간의 단축 및 비용 절감하는데 목표를 둔다. 일반 PC에서 COM 포트를 이용하는 시리얼 통신으로 테스트 킷을 구현하여 드라이버를 개발하고 테스트할 수 있으며. 나아가 드라이버 연구에 있어서 실제 타겟 디바이스 없이 S/W 만으로도 올바른 드라이버를 개발할 수 있으며, 드라이버 동작과 내부 메커니즘을 비주얼하게 확인하여 초보 드라이버 개발자들에게도 도움을 주는데 목적이 있다. 이에 본 연구에서 새로운 개발 방향을 제시하고 실험을 하였다.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.6
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• pp.837-842
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• 2010

In this paper, quantum cryptography systems used in the design process inevitably open bit stream of pseudo-random number that exists multiple open channels between them and the need to share information on the part of the situation exposes a pair of bit stream. In this paper, the base test of pseudo-random number I tested out this process and the merge bit binary column look out for randomness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.4
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• pp.775-782
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• 2006

We generated blocks from the direction-extracted fingerprint during the pre-process of the fingerprint recognition algorithm and performed training by using the direction minutiae of each block as the input pattern of the neural network, so that we extracted the core points to use in the matching. Based on this, we designed the fingerprint recognition embedded system and tested it using the control board and the serial communication to utilize it for a variety of application systems. As a result, we can verify the reliance satisfactorily.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2904-2906
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• 2000

본 논문에서는 반도체 제조 공정에서 장비와 호스트간에 통신을 할 수 있는 SECS(SEMI Equipment Communications Standard) 프로토를의 개발을 제안한다. SECS 프로토콜은 메시지 전송을 위한 헤더 부분을 정의하는 SECS-I 프로토콜과 메시지 내용을 정의하는 SECS-II 프로토콜로 나뉘어지는데, RS232 시리얼 통신을 하는 SECS-I 프로토콜 대신에 이더넷(ethernet)을 통해 TCP/IP 통신을 할 수 있는 HSMS 프로토콜을 구현하고자 한다. HSMS(High-speed SECS Message Services)프로토콜은 SECS-I과 마찬가지로 SECS-II 메시지 내용을 전송 할 수 있도록 10바이트 크기의 헤더로 정의된다. HSMS 프로토콜 통신은 TCP/IP를 기반으로 하기 때문에 SECS 메시지 전송을 위한 통신 선로를 설정하기 위해 소켓 API를 응용하고 항상 통신 대기상태를 유지하기 위해 데몬(daemon) 형태로 구성한다. 실제 메시지 내용을 정의하고 있는 SECS-II 프로토콜은 데이터 인덱스 테이블과 표준에 정의된 형식에 맞게 파일형태나 DLL(Dynamic Link Library)형태로 구성하고 프로세스 프로그램(process program)을 수행하기 위해 SECS 프로토콜 표준에서 정의하는 SML(SECS Message Language)형식으로 변환 할 수 있는 스크립트 변환기(script translator)를 구현한다. 또한 HSMS 프로토콜이 전송할 SECS-II 메시지를 저장하기 위한 파라미터를 정의하고 실제 통신을 위한 테스트 베드를 위한 응용 프로그램을 제작한다

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.3
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• pp.703-713
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• 2015

The linking system between the control system and the field devices in the existing EMS/SCADA, in order to increase the reliability of the data, and access control through the separation of external network. Currently, There is a tendency that the need for connection to an external network that takes into account the economic aspect, systematic management and efficiency of operations is increasing. Such is evolved linkage section, is to have more security vulnerabilities than in the past, Eventually communication EMS/SCADA linkage section requires special management method. In this paper, taking into account the domestic environment, were presented the security Certification and Accreditation technology that was applied to serial DNP3 and TCP/IP based DNP3 that are mainly used in EMS/SCADA linkage section. Presented to security of Certification and Accreditation technology, divided into Resource Robustness Test and Malicious Packet Test for evaluate the safety. Each of the security requirements and evaluation method in proposed technology, is an attempt to present the differentiation of the existing Certification and Accreditation technology.

• Smart Media Journal
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• v.9 no.3
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• pp.107-115
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• 2020

Recently, BIM has become mandatory in the construction field, research on various use cases is increasing. In particular, when virtual reality technology, one of the core technologies of the 4th industrial revolution, and BIM are combined, it can be used in various fields such as preliminary design review and construction simulation. Until now, however, virtual reality grafting technology is only used as a simple prototype or as a model house. Also, it is difficult to activate virtual construction because it is expensive to produce high-quality virtual reality contents. Therefore, in this paper, in order to increase the utilization and quality of the virtual construction field, a study was conducted to shorten the material mapping time, which takes a lot of time when producing virtual reality contents using BIM. To this end, object properties were assigned to enable material mapping in the BIM model, and materials most used in the construction field were configured, and automated material function development and final tests were conducted that automatically map properties and materials. For the test, 10 models were used and the test was repeated three times, and the productivity improvement of about 50.16% was finally achieved. In the future, we plan to conduct research on physical data weight reduction based on the advanced material mapping automation function and the large-capacity BIM model.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.