• Journal of Digital Contents Society
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• v.6 no.1
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• pp.41-48
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• 2005

In this paper, we propose and evaluate symbol timing recovery algorithm for S-DMT cable modern, which supports more channels and better quality symmetric mutimedia service over HFC network. We adopt timing recovery algorithm of PN sequence insertion in time domain and evaluate the performance of it in various noise channel such as AWGN, ISI, impulse. We verified that performance of this algorithm is depends on the channel noise environment and sampling clock offset and that over 10 dB degradation of Eb/No is occurred at the timing failure probability of $10^3$ in the composite noise channel of AWGN, ISI, and impulse in comparison with impulse noise-alone channel. finally, we verified that this algorithm showed good timing failure probability in case of sampling clock optimization was performed in advance.

• Journal of the Korean Society for Railway
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• v.15 no.5
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• pp.454-458
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• 2012

The CBTC(Communication based Train Control) and WPAN(Wireless Personal Area Network) systems employed on 2.4GHz ISM band wireless networks provide complementary service within the same environment. Coexistence between the networks will be impaired if the mutual packets are uncertainty associated the timing or gaussian distance. This paper analyzes the impact of the mutual interference and proposed method to minimize the effect of the WPAN system signals on CBTC system. The performance analysis is illustrated by examining the symbol error rate versus signal to noise interference ratio in terms of carrier frequency offset. The method contributes to reduce the symbol error rate drastically. However it can't be a fundamental solution for the impact on the interference problem. It may be needed for railway only frequency after checking the problems of the current railway frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.880-883
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• 2002

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFFT after the getting the frequency, response of deducted channel from channel deductor of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of $\pm$1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.10A
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• pp.922-929
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• 2005

This paper proposes an adaptive pilot beacon equipment for mobile communication systems based on direct spread spectrum technology which generates the pilot channel for handoff between base stations by using the information acquired from the downstream wireless signal regarding the overhead channel information. Such an adaptive pilot beacon equipment will enable low power operation since among the wireless signals, only the pilot channel will be generated and transmitted. The pilot channel in the downstream link of the CDMA receiver is used to acquire time and frequency synchronization and this is used to calibrate the offset for the beacon, which implies that time synchronization using GPS is not required and any location where forward receive signal can be received can be used as the installation site. The downstream link pilot signal searching within the CDMA receiver is performed by FPGA and DSP. The FPGA is used to perform the initial synchronization for the pilot searcher and DSP is used to perform the offset correction between beacon clock and base station clock. The CDMA transmitter the adaptive pilot beacon equipment will use the timing offset information in the pilot channel acquired from the CDMA receiver and generate the downstream link pilot signal synchronized to the base station. The intermediate frequency signal is passed through the FIR filter and subsequently upconverted and amplified before being radiated through the antenna.

• Journal of Broadcast Engineering
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• v.24 no.3
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• pp.463-471
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• 2019

This paper proposes a method for reducing the complexity of LIC (Local Illuminance Compensation) for bi-directional inter prediction. The LIC performs local illumination compensation using neighboring reconstruction samples of the current block and the reference block to improve the accuracy of the inter prediction. Since the weight and offset required for local illumination compensation are calculated at both sides of the encoder and decoder using the reconstructed samples, there is an advantage that the coding efficiency is improved without signaling any information. Since the weight and the offset are obtained in the encoding prediction step and the decoding step, encoder and decoder complexity are increased. This paper proposes two methods for low complexity LIC. The first method is a method of applying illumination compensation with offset only in bi-directional prediction, and the second is a method of applying LIC after weighted average step of reference block obtained by bidirectional prediction. To evaluate the performance of the proposed method, BD-rate is compared with BMS-2.0.1 using B, C, and D classes of MPEG standard experimental image under RA (Random Access) condition. Experimental results show that the proposed method reduces the average of 0.29%, 0.23%, 0.04% for Y, U, and V in terms of BD-rate performance compared to BMS-2.0.1 and encoding/decoding time is almost same. Although the BD-rate was lost, the calculation complexity of the LIC was greatly reduced as the multiplication operation was removed and the addition operation was halved in the LIC parameter derivation process.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.4 no.3
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• pp.5-12
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• 2005

In wire discharge machining which is using STD 11 as die materials, the major factors of machining speed are discharge voltage, discharge current, and discharge time. All of the three factors give the effect. Increasing of the discharge pulse time gets groove width wider and it relatively increases surface roughness and clearance. If no load voltage is decreased, surface roughness is good but it decreases machining speed. If on time is increased, machining speed will get faster and clearance and offset value also get bigger.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2152-2154
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• 2002

신경망을 이용한 적응제어는 학습능력에 따라 외란작용에 스스로 대처하고, 정밀한 제어가 가능하지만 학습파라미터가 최적화되기 전에는 불안정한 제어응답을 보인다. 퍼지논리는 전문가의 경험을 논리화한 것으로 제어특성은 좋으나, 외란에 대한 적응력이 부족하여 계속적인 오프셋이 발생할 수 있다. 따라서, 퍼지와 신경망을 시스템의 동특성에 따라 혼용한 제어방식을 제시하고, 시뮬레이션으로 시간지연이 있는 CSTH의 온도와 비선형 공정인 pH 중화공정에 적용하여 단순신경망 제어어보다 개선된 제어응답 특성을 얻었다.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.21-23
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• 2018

본 논문에서는 능동형 스너버를 사용한 비대칭 하프-브리지 컨버터를 제안한다. 비대칭 하프-브리지 컨버터는 홀드-업 시간을 고려하여 넓은 입력전압 범위에서 설계되면, 노미널 동작 시 작은 시비율로 동작하여 변압기에 큰 오프셋 전류가 발생한다. 또한 변압기가 작은 턴 비로 설계되어 1차측 전류 스트레스와 2차측 정류기의 전압 스트레스가 커지는 문제점이 있다. 이러한 문제점들을 해결하기 위해, 제안하는 컨버터에서는 추가 스위치를 사용해 추가적인 전압이득을 얻음으로써, 홀드-업동작 시 낮아지는 입력 전압을 보상한다. 때문에 제안하는 컨버터는 홀드-업 상태를 고려하지 않고 설계될 수 있어, 노미널 시에 큰 시비율로 동작한다. 게다가 추가 스위치는 능동형 스너버로 사용되어 2차측 정류기 다이오드의 전압 링잉을 제거하여 전압 스트레스를 저감시킨다. 이와 같은 특징으로 인하여 제안하는 컨버터는 전 부하 영역에서 높은 효율을 갖는다. 제안하는 컨버터의 효용성을 검증하기 위해 320-410V 입력전압과 19.5V/200W 출력에서 실험이 진행되었다.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.138-139
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• 2014

3레벨 NPC 인버터는 구조상 DC Link가 두 개의 커패시터로 직렬 구성되어 있어 두 커패시터 간의 전압 불균형의 문제가 발생한다. 중성점의 변동으로 인하여 스위치 소자의 소손과 제어기의 오작동 등 시스템의 안정도가 떨어지게 된다. 기존의 중성점 전압을 제어하는 오프셋 전압 인가 방식은 zero point 지점에서 불연속 스위칭 구간이 존재하기 때문에 중성점 제어가 불가능하다. 본 논문에서는 중성점 전압을 제어하기 위하여 DPWM 기법에서 중성점 전압을 제어하는 방식을 제안하였다. DC Link의 두 커패시터 전압 불균형이 발생하면 $60^{\circ}(+30^{\circ})$ DPWM 기법으로 Positive 벡터와 Negative 벡터의 스위칭 인가 시간을 조절하여 두 커패시터의 전압 균형을 이루게 한다. 시뮬레이션을 통하여 본 논문에서 제안한 방식에 대한 타당성을 검증하였다.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.486-487
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• 2014

본 논문은 멀티레벨 인버터를 이용한 무정전 전원장치 시스템 (UPS; Uninterruptible Power Supply)의 신뢰성 향상을 위한 중성점 전압 불평형 제어 기법을 제안한다. 무정전 전원장치 시스템 (UPS)은 불평형 부하조건 시 직류단에 전압 불평형이 발생되며 이는 출력 전류의 왜곡을 일으켜, 민감한 부하에 손상을 입힐 수 있다. 제안한 제어기는 커패시터 전압 측정을 통해 시간오프셋을 추정한 후 공간 벡터 변조 방식의 변형 없이 중성점 전압 불평형을 제어하여, 직류단의 전압을 평형상태로 유지한다. 또한, 100kW급 UPS 시스템 시뮬레이션 검증을 통해 제어기의 타당성을 입증하였다.