• Title/Summary/Keyword: 시간동기

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Finite Control Set Model Predictive Control with Variable Sampling Time for Torque Ripple Reduction in SPMSM drive system (표면부착형 영구자석 동기 전동기 구동 시스템에서 토크 리플 저감을 위한 가변 샘플링 시간이 적용된 유한요소 모델예측제어)

  • Lee, Jae-Hyung;Choo, Kyoung-Min;Jeong, Won-Sang;Won, Chung-Yuen
    • Proceedings of the KIPE Conference
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    • 2019.07a
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    • pp.396-397
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    • 2019
  • 본 논문은 유한요소 모델예측제어(FCS-MPC)의 샘플링 시간을 가변하여 표면부착형 영구자석 동기 전동기(SPMSM)의 토크 리플을 개선하고 스위칭 손실을 저감하는 가변 샘플링 시간이 적용된 모델예측제어 기법을 제안한다. 기존 FCS-MPC는 토크 리플을 저감하기 위해 고정 샘플링 시간을 짧게 설정하였다. 고정 샘플링 시간을 짧게 설정함에 따라, 전압벡터의 변경횟수가 증가하여 스위칭 손실이 증가하였다. 본 논문은 이러한 문제점을 해결하기 위해 가변 샘플링 시간이 적용된 FCS-MPC를 통해 토크 리플을 저감하고, 전압벡터의 변경횟수를 감소시켜 스위칭 손실을 저감하였다. 본 논문에서 제안하는 기법은 시뮬레이션을 통해 증명되었다.

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The Development of Protocol for Construction of Smart Factory (스마트 팩토리 구축을 위한 프로토콜 개발)

  • Lee, Yong-Min;Lee, Won-Bog;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.23 no.3
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    • pp.1096-1099
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    • 2019
  • In this paper, we propose the protocol for construction of smart factory. The proposed protocol for construction of smart factory consists of an OPC UA Server/Client, a technology of TSN realtime communication, a NTP & PTP time synchronization protocol, a FieldBus protocol and conversion module, a technology of saving data for data transmit latency and synchronization protocol. OPC UA server/client is a system integration protocol which makes interface industrial hardware device and supports standardization which allows in all around area and also in not independent from any platform. A technology of TSN realtime communication provides an high sensitive time management and control technology in a way of sharing specific time between devices in the field of high speed network. NTP & PTP time synchronization protocol supports IEEE1588 standardization. A fieldbus protocol and conversion module provide an extendable connectivity by converting industrial protocol to OPC. A technology of saving data for data transmit latency and synchronization protocol provide a resolution function for a loss and latency of data. Results from testing agencies to assess the performance of proposed protocol for construction of smart factory, response time was 0.1367ms, synchronization time was 0.404ms, quantity of concurrent access was 100ea, quantity of interacting protocol was 5ea, data saving and synchronization was 1,000 nodes. It produced the same result as the world's highest level.

Time-to-Digital Converter Using Synchronized Clock with Start and Stop Signals (시작신호 및 멈춤신호와 동기화된 클록을 사용하는 시간-디지털 변환기)

  • Choi, Jin-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.5
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    • pp.893-898
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    • 2017
  • A TDC(Time-to-Digital Converter) of counter-type is designed by $0.18{\mu}mCMOS$process and the supply voltage is 1.5 volts. The converted error of maximum $T_{CK}$ is occurred by the time difference between the start signal and the clock when the period of clock is $T_{CK}$ in the conventional TDC. And the converted error of -$T_{CK}$ is occurred by the time difference between the stop signal and the clock. However in order to compensate the disadvantage of the conventional TDC the clock is generated within the TDC circuit and the clock is synchronized with the start and stop signals. In the designed TDC circuit the conversion error is not occurred by the difference between the start signal and the click and the magnitude of conversion error is reduced (1/2)$T_{CK}$ by the time difference between the stop signal and the clock.

A Synchronous/Asynchronous Hybrid Parallel Power Iteration for Large Eigenvalue Problems by the MPMD Methodology (MPMD 방식의 동기/비동기 병렬 혼합 멱승법에 의한 거대 고유치 문제의 해법)

  • Park, Pil-Seong
    • The KIPS Transactions:PartA
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    • v.11A no.1
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    • pp.67-74
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    • 2004
  • Most of today's parallel numerical schemes use synchronous algorithms, where some processors that have finished their tasks earlier than others must wait at synchronization points for correct computation. Hence overall performance of the system is dependent upon the speed of the slowest processor. In this paper, we det·ise a synchronous/asynchronous hybrid algorithm to accelerate convergence of the solution for finding the dominant eigenpair of a large matrix, by reducing the idle times of faster processors using MPMD programming methodology.

Design and Implementation of a SMIL Player (SMIL(Synchronized Multimedia Integration Language) Player의 설계 및 구현)

  • 유초롱;김은영;권택근
    • Proceedings of the Korean Information Science Society Conference
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    • 2000.10c
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    • pp.446-448
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    • 2000
  • 오늘날 멀티미디어 프리젠테이션에 대한 관심이 급증하면서 많은 사용자들이 텍스트 서비스뿐 아니라 이미지나 오디오, 동영상 데이터를 전송하거나 받을 수 있는 서비스를 요구한다. 이에 따라 멀티미디어를 통합 표현하기 위한 요구가 확산되어 XML에 기반을 둔 SMIL 이라는 멀티미디어 동기화 언어가 등장하게 되었다. SMIL은 오디오, 비디오, 이미지, 텍스트 등의 다양한 미디어 데이터들을 SMIL 문서 안에 하나의 시나리오로 동기화 하여 프리젠테이션 할 수 있게 한다. SMIL이 제공하는 동기화는 미디어들의 공간적인 배치에 따른 동기화와 프리젠테이션 시간에 따른 동기화로 나뉜다. 멀티미디어의 동기화를 위한 표준 언어인 SMIL은 사용자가 보다 편리하게 멀티미디어를 동기화하고 프리젠테이션 할 수 있도록 한다. 본 논문에서는 SMIL 1.0 권고안을 따르고 사용자들이 보다 쉽게 사용할 수 있는 SMIL 플레이어를 설계 및 구현하고자 한다.

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Robust Code Acquisition System in Rayleigh Fading Channel (Rayleigh 페이딩 채널에서 강인한 동기 획득 시스템)

  • 장경운;김기채;박용완
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.11 no.5
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    • pp.723-730
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    • 2000
  • In this paper, we perform a performance analysis of serial acquisition scheme using AWGN rejection filter in Rayleigh fading channel and propose robust acquisition scheme using Reference filter, which is utilized to vary threshold at fading rate, in Rayleigh fading channel. AWGN rejection filter is utilized to evaluate running average for compensating channel gain. The JAKE model, which a channel model, is used for the analysis. The simulation result shows that the mean acquisition time of the proposed acquisition system is minimized than acquisition system using AWGN rejection filter and serial-search acquisition system.

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Analysis of the range estimation error of a target in the asynchronous bistatic sonar (비동기 양상태 소나의 표적 거리 추정 오차 분석)

  • Jeong, Euicheol;Kim, Tae-Hwan
    • The Journal of the Acoustical Society of Korea
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    • v.39 no.3
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    • pp.163-169
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    • 2020
  • The asynchronous bistatic sonar needs to estimate direct blast arrival time at a receiver to localize targets, and therefore the direct blast arrival time estimation error could be added to target localization error in comparison with synchronous system. Direct blast especially appears as several peaks at the matched filter output by multipath, thus we compared the first peak detection technique and the maximum peak detection technique of those peaks for direct blast arrival time estimation through sea trial data. The test was performed in a shallow sea with bistatic sonar made up of spatially separated source and line array sensors. Line array sensors obtained the target signal which is generated from the echo repeater. As a result, the first peak detection technique is superior to maximum peak detection technique in direct blast arrival time estimation error. The result of this analysis will be used for further research of target tracking in the asynchronous bistatic sonar.

Analysis of Delay time by Adjusting of Check Interval in Asynchronous Wireless Sensor Network with Low Power (저전력 비동기 무선센서네트워크에서 체크인터벌 조절에 따른 지연시간 분석)

  • Yoon, Mi-Hee;Kim, Dongwon
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.2
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    • pp.75-80
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    • 2020
  • There are so many low power MAC protocols for wireless sensor network. IEEE802.15.4 among them has disadvantage of a large power consumption for synchronization. To save power consumption it use the superframe operation alternating sleep mode and awake mode. But latency is longer result from superframe operation. B-MAC can have shorter latency according to check interval. But transmitter consumes more power because of long preamble. And receiver is suffering from overhearing. In this paper, we use the adaptive check interval scheme[1] of B-MAC for enhancing the power consumption. Its maximum throughput and minimum delay is evaluated by comparing the proposed scheme with a typical single channel IEEE802.15.4.

Instruction-level Power Model for Asynchronous Processor, A8051 (비동기식 프로세서 A8051의 명령어 레벨 소비 전력 모델)

  • Lee, Je-Hoon
    • The Journal of the Korea Contents Association
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    • v.12 no.7
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    • pp.11-20
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    • 2012
  • This paper presents new instruction-level power model for an asynchronous processor, A8051. Even though the proposed model estimates power consumption as instruction level, this model reflects the behavioral features of asynchronous pipeline during the program is executed. Thus, it can effectively enhance the accuracy of power model for an asynchronous embedded processor without significant complexity of power model as well as the increase of simulation time. The proposed power model is based on the implementation of A8051 to reflect the characteristics of power consumption in A8051. The simulation results of the proposed model is compared with that of gate-level synthesized A8051. The proposed power model shows the accuracy of 94% and the simulation time for estimation the power consumption was reduced to 1,600 times.

Effects of Multiple Threshold Values for PN Code Acquisition in DS-CDMA Systems (PN 코드 동기획득에서 다중 임계치의 효과)

  • Lee, Seong-Ju;Kim, Jae-Seok
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.39 no.1
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    • pp.42-48
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    • 2002
  • In this paper, a decision method using multiple threshold values for PN code acquisition in Direct Sequence Code Division Multiple Access (DS-CDMA) systems is described. We apply this technique to the conventional double dwell serial search algorithm and analyze it in terms of mean code acquisition time. For the analysis, we present mathematical model of proposed algorithm and also perform the simulation under IMT-2000 channel models. Numerical results show that our proposed scheme outperforms the conventional one by 0.2 - 0.5 sec with respect to the mean code acquisition time because multiple threshold values mitigate the possible decline in search performance caused by the use of a single threshold.