• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.105-111
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• 2013

We have developed an analog associative memory implemented with an analog array which has linear writing and erasing characteristics. The associative memory adopts a winner-take-all strategy. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density. A multiple memory cell configuration is also presented for achieving higher integration density, quick readout, and fast writing. The system technology presented here is ideal for a real time recognition system. We simulate the function of the mechanism by menas of Hspice with $1.2{\mu}$ double poly CMOS parameters of MOSIS fabrication process.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.3
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• pp.357-364
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• 2015

This research presents a DC-DC converter controller implemented with an analog memory. The structure of the converter will contribute to solve the stability problem unavoidable in a conventional closed loop converter. The analog memory will be used for realizing CAM(Contents Addressable Memory) which contains the output of the converter and the relevant duty ratio, respectively. The operation for reading in the memory is executed with an absolute differencing circuit and a WTA(Winner-Take-All) circuit suitable for a nearest-match function of the CAM. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density.