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http://dx.doi.org/10.13067/JKIECS.2015.10.3.357

Design of DC-DC converter controller implemented with analog memory  

Chai, Yong-Yoong (계명대학교 전자공학과)
Do, Wang-Lok (계명대학교 전자공학과)
Publication Information
The Journal of the Korea institute of electronic communication sciences / v.10, no.3, 2015 , pp. 357-364 More about this Journal
Abstract
This research presents a DC-DC converter controller implemented with an analog memory. The structure of the converter will contribute to solve the stability problem unavoidable in a conventional closed loop converter. The analog memory will be used for realizing CAM(Contents Addressable Memory) which contains the output of the converter and the relevant duty ratio, respectively. The operation for reading in the memory is executed with an absolute differencing circuit and a WTA(Winner-Take-All) circuit suitable for a nearest-match function of the CAM. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density.
Keywords
Programming Voltage; WTA; Content Addressable Memory; DC-DC Converter; Controller;
Citations & Related Records
Times Cited By KSCI : 5  (Citation Analysis)
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1 E. Nho, Power Electronic, Seoul Korea: munundang, 2011.
2 H. Kim, Switch mode Power supply, Paju Korea: BMsungandang, 2012.
3 K. Lee, "Design and Implementation of a Current Controller for Boost Converters Using a DSP," The Korean Institute of Power Electronics, vol. 17, no. 3, 2012, pp. 259-265.   DOI   ScienceOn
4 L. Guo, and J.-Y. Hung, and R.-M. Nelms, "Evaluation of DSP-Based PID and Fuzzy Controllers for DC-DC Converters," IEEE Trans. Industrial Electronics, vol. 56, no. 6, 2009, pp. 2237-2248.   DOI
5 Y. Chai, "An Analog Content Addressable Memory implemented with a Winner-Take-All Strategy," J. of the Korea Institute of Electronic Communication Science, vol. 8, no. 1, pp. 105-111.   DOI
6 J. Guerrieri, "Low power analog absolute differencing circuit and architecture," US patents, patent No. US5438293, 1995.
7 L. G. Johnson, "MOS implementation of winner-Take-All network with application to content-addressable memory," Electronics Letters, vol. 27, no. 11, 1991, pp. 957-958.   DOI
8 S. Ahn, D. Kim, O. Kwon, Y. Bae, and J. Lee, "Analysis on the Dynamics of Keyword Mapping for Detecting Emerging Technologies : A Case Study on Graphene," J. of the Korea Institute of Electronic Communication Science, vol. 7, no. 6, 2012, pp. 1393-1492.   DOI
9 K. Yoon and Y. Chai, "Enhancement of Data Retention Time in DRAM through Optimization of Sidewall Oxidation," J. of the Korea institute of Electronic Communication Science, vol. 7, no. 4, 2012, pp. 833-838.   DOI
10 S. Bae and J. Han, "Object Oriented Fault Detection for Fault Models of Current Testing," J. of the Korea Institute of Electronic Communication Science, vol. 5, no. 4, 2010, pp. 443-449.