• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.347-356
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• 2003

The OCT algorithm needs efficient hardware architecture to compute inner product. The conventional methods have large hardware complexity. Because of this reason. a computation sharing multiplier was proposed for implementing inner product. However, the existing multiplier has inefficient hardware architecture in precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we proposed a new efficient computation sharing multiplier and applied it to implementation of 1-D DCT processor. The comparison results show that the new multiplier is more efficient than an old one when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using the proposed multiplier is more high performance than typical design methods.

• ETRI Journal
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• v.13 no.2
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• pp.9-14
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• 1991

직병렬 승산기는 피승수와 승수중 어느 하나가 병렬로 입력되고 또다른 수는 직렬로 입력되는 구조를 가지며, 디지틀 신호처리, 온라인 응용, 특수 목적용 계산 시스팀 등에서 많이 이용되고 있다. 본 논문에서는 2 의 보수를 위한 직병렬 승산기의 논리구조를 제안한다. 제안한 2의 보수 직병렬 승산기는 효과적인 2의 보수 직병렬 승산 알고리즘에 의해서 모든 데이터 신호가 국부적 연결만으로 구성되며, 간단하고 모듈화된 하드웨어의 구성으로 쉽게 설계할 수 있다. 이 승산기는 무부호 승산과 마찬가지로 2n+1 사이클만을 필요로 하고, 각 사이클 시간은 무부호 직병렬 승산에 비해서 2의 보수 승산을 위한 XOR 게이트의 지연시간이 추가된 것뿐이다. 또한, 제안한 2의 보수 직병렬 승산기는 VLSI 구현에 매우 적합한 구조를 지닌다.

• Journal of the Korean Data and Information Science Society
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• v.10 no.1
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• pp.29-36
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• 1999

We propose a new method of asymptotic inference on the odds ratio (or cross-product ratio) in $2{\times}2$ contingency table. Saddlepoint approximations to the conditional tail probability we used in this procedure. We assess the accuracy of the suggested method by comparing with the exact one. To obtain the exact values, we need very complicated calculations containing the cumulative probabilities of non-central hypergeometric distribution. The suggested method in this paper is very accurate even for small or moderate sample sizes as well as simple and easy to use. Example with a real data is also considered.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.617-620
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• 2001

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier that receives two N-bit numbers and produces an N-bit product by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance (truncation error, area) was analyzed. Since the truncated Booth multiplier omits about half the partial product generators and adders, it has an area reduction by about 35%~40%, compared with non-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 30%~40%, compared with conventional methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.323-329
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• 2002

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier which produces an N-bit output from a two's complement multiplication of two N bit inputs by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance(truncation error, area) was analyzed. Since the truncated Booth multiplier does not have about half the partial product generators and adders, it results an area reduction of about 35％, compared with no-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 60％, compared with conventional methods. A 16-b$\times$16-b truncated Booth multiplier core is designed on full-custom style using 0.35-${\mu}{\textrm}{m}$ CMOS technology. It has 3,000 transistors on an area of 330-${\mu}{\textrm}{m}$$\times$262-${\mu}{\textrm}{m}$ and 20-㎽ power dissipation at 3.3-V supply with 200-MHz operating frequency.

• Journal of Korean Society of Transportation
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• v.35 no.4
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• pp.307-320
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• 2017

The objective of this study is to identify the effectiveness of ESC(Electronic Stability Control) based on a meta analysis technique. Accident Rate, Fatal Crash Rate, Loss of Control Crash Rate were set as indexes of traffic safety evaluation. Also, reviews on the effectiveness of ESC were collected using keyword, 'ESC'. As a result, the Effect size of accident rate odd ratio was 0.90. When ESC system was applied on vehicles, accident rate decreased by 10%. Also, the Effect size of fatal crash rate odd ratio was 0.64. When ESC system was applied on vehicles, fatal crash rate decreased by 36%. Lastly, the Effect size of loss of control crash rate odd ratio was 0.73. When ESC system was applied on vehicles, loss of control crash rate decreased by 27%. The outcome of this study would be effectively used for developing polices and regulations for ESC installation obligation of commercial vehicles.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.1143-1150
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• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed using a $0.25-\mum$ 5-metal CMOS technology. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles. The DMM consists of a $28-b\times28-b$ single-precision multiplier designed using radix-4 Booth receding and redundant binary (RB) arithmetic, an accumulator and a simple control logic for mode selection. It contains about 25,000 transistors on the area of about $0.77\times0.40-m^2$. The HSPICE simulation results show that the DMM core can safely operate with 200-MHZ clock at 2.5-V, and its estimated power dissipation is about 130-㎽ at double-precision mode.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.235-239
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• 1989

A multiplier is proposed for computing multiplication of two arbitrary elements in the finite fields GF($2^m$), and the operation process is described step by step. The modified type of the circuit which is constructed with m-stage feedgack shift register, m-1 flip-flop, m AND gate, and m-input XOR gate is presented by referring to the conventional shift-register multiplier. At the end of mth shift, the shift-register multiplier stores the product of two elements of GF($2^m$); however the proposed circuit in this paper requires m-1 clock times from first input to first output. This circuit is simpler than cellulra-array or systolic multiplier and moreover it is faster than systolic multiplier.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.9-15
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• 2003

An optimized finite-field multiplier is proposed for encryption and error correction devices. It is based on a modified Linear Feedback Shift Register (LFSR) which has lower power consumption and smaller area than prior LFSR-based finite-field multipliers. The proposed finite field multiplier for GF(2n) multiplies two n-bit polynomials using polynomial basis to produce $z(x)=a(x)^*b(x)$ mod p(x), where p(x) is a irreducible polynomial for the Galois Field. The LFSR based on a serial multiplication structure has less complex circuits than array structures and hybrid structures. It is efficient to use the LFSR structure for systems with limited area and power consumption. The prior finite-field multipliers need 3${\cdot}$m flip-flops for multiplication of m-bit polynomials. Consequently, they need 6${\cdot}$m latches because one flip-flop consists of two latches. The proposed finite-field multiplier requires only 4${\cdot}$m latches for m-bit multiplication, which results in 1/3 smaller area than the prior finite-field multipliers. As a result, it can be used effectively in encryption and error correction devices with low-power consumption and small area.

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.969-973
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• 1995

In this paper, a new parallel Multiplier array is proposed to reduce the multiplication time by modifying CAS(carry select adder) cell structure used in the conventional parallel multiplier array. It is named MCSA(modified CSA) that assignes the addend and augend to the inputs of CSA faster than Ci(carry input). Also the designed DCSA (doubled inverted input CSA) is appended after the last product term for the carry propagation adder. The proposed scheme is designed with MCSA and DCSA, and simulated. It is verified that the circuit size is increased about 13% compared with the conventional multiplier array with CSA cell but the operation time is reduced about 52%.