• Convergence Security Journal
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• v.10 no.2
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• pp.19-26
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• 2010

In this study, we try to make up for the vulnerability in steganography that it is easily revealed the hidden logo image in cover image by bit-plane extraction. For this, we apply some methods, the permutation which shift the scattered pieces of logo image to one side, bit-plane dispersion insertion method and pack-type compressor.

• The KIPS Transactions:PartC
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• v.8C no.1
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• pp.12-15
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• 2001

A summation generator creates sequence from addition with carry of LFSR (Linear Feedback Shift Register) sequences. Similarly, it is possible to generate keystream by bitwise exclusive-oring on two FCSR sequences. In this paper, we described the cryptographic properties of a sequence generated by the FCSRs.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.7 no.3
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• pp.121-125
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• 2014

A hardware implementation of Hilbert transform is indespensible element in DSP system, but it suffers form a high complexity of system level hardware resulted in a large amount of the used gate. In this paper, we implemented the Hilbert transformer using MAG algorithm that reduces the complexity of hardware.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.494-497
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• 2004

계통연계형 태양광발전 시스템의 확대보급에 따라 단독운전 검출기법의 검출 성능에 대한 검증의 필요성이 대두되고 있다. 본 논문에서는 단독운전 검출기법의 대표적인 능동적 검출기법인 무효전력 변동기법 (reactive power variation method)과 주파수 쉬프트기법(active frequency drift method)을 IEEE Std 929-2000에서 명시된 단독운전검출 시험 방법을 이용하여 단독운전검출기법의 성능 및 불검출 영역(non-detection zone)에 대하여 비교 분석하였다.

• The KIPS Transactions:PartB
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• v.11B no.7 s.96
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• pp.779-784
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• 2004

In this paper, we have proposed an image contrast control method using brightness preserving on the FPD(Flat Panel Display). The proposed method can be easily applied to the FPD required real-time processing, since hardware complexity is greatly reduced using linear approximation method of CDF(Cumulative Density Function). For effective processing of the proposed algorithm, we have utilized the sample value of CDF and Barrel Shift. Visual test and standard deviation of their histogram have been introduced to evaluate the resultant output images of the pro-posed method and the original ones.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.89-93
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• 2002

This paper describes an ALU core which is suitable for 32-bit DSP This ALU operates in 32-bit data and occupies the third stage, execution, among 5 stage pipeline structure. The supplied functions of the ALU are arithmetic operations, logical operations, shifting, and so on. For the implementation of this ALU core, each functional block is described by HDL. And the functional verification of the ALU core is performed through HDL simulation. This ALU is designed to use the 32-bit DSP.

• Proceedings of the KIEE Conference
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• 1992.07a
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• pp.459-461
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• 1992

This paper presents the new method to recognize the 2D patterns dynamically by rotating the input patterns according to the difference vector. Generally neural network with many patterns leads to various recognition ratio. The dynamic management of input patterns means that we can move pixels to desired locations controlled by the difference vector. We divide dual neural network model into two parts at learning phase, respectively. And then we combine them to construct the total network. Our model has some good results such that it has less number of patterns and reduced learning time. At present, we only discuss the four way movement of input patterns. The research for the complex movement will be fulfilled later.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1205-1208
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• 2003

본 논문에서는 분할된 스캔을 이용한 저전력 BIST 구조를 제안한다. 제안하는 BIST는 내부 스캔 패스를 회로의 구조적인 정보와 테스트 패턴 집합의 특성에 따라 4개의 스캔 패스로 분할하고 일부 스캔 패스에만 입력패턴이 인가되도록 설계하였다. 따라서 테스트 패턴 입력 시에 스캔 패스로의 쉬프트 동작 수를 줄임으로써 회로 내부의 전체 상태천이 수를 줄일 수 있다. 또한 4개로 분할되는 스캔패스의 길이를 고려하여 각 스캔 패스에 대해 1/4의 속도로 낮춰진 테스트 클럭을 인가함으로써 전체 회로의 전력 소모를 줄일 수 있도록 하였다. ISCAS89 벤치마크 회로에 대한 실험을 통하여 제안하는 BIST 구조가 기존 BIST 구조에 비해 최대 21%까지 전력소모를 줄일 수 있음을 확인하였다.

• Journal of the Korea Computer Industry Society
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• v.2 no.9
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• pp.1183-1190
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2C
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• pp.123-129
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• 2006

In this paper, we concentrate on reducing the complexity for efficient encoder. We design structural LDPC code using circulant matrix and permutation matrix and eIRA code. It is possible to design low complex encoder by using shift register and differential encoder and interleaver than general LDPC encoder that use matrix multiplication operation. The code designed by this structure shows similar performance as random code. And the proposed codes can considerably reduce a number of XOR gates.