• Journal of Korean Society of Steel Construction
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• v.10 no.3 s.36
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• pp.473-486
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• 1998

A numerically stable technique to remove the limitation in choosing a shift in the subspace iteration method with shift is presented. A major difficulty of the subspace iteration method with shift is that because of singularity problem, a shift close to an eigenvalue can not be used, resulting in slower convergence. This study solves the above singularity problem using side conditions without sacrifice of convergence. The method is always nonsingular even if a shift is an eigenvalue itself. This is one of the significant characteristics of the proposed method. The nonsingularity is proved analytically. The convergence of the proposed method is at least equal to that of the subspace iteration method with shift, and the operation counts of above two methods are almost the same when a large number of eigenpairs are required. To show the effectiveness of the proposed method, two numerical examples are considered.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.12 no.3
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• pp.371-383
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• 1999

An efficient and numerically stable eigensolution method for structures with multiple natural frequencies is presented. The proposed method is developed by improving the well-known subspace iteration method with shift. A major difficulty of the subspace iteration method with shift is that because of singularity problem, a shift close to an eigenvalue can not be used, resulting in slower convergence. In this paper, the above singularity problem has been solved by introducing side conditions without sacrifice of convergence. The proposed method is always nonsingular even if a shift is on a distinct eigenvalue or multiple ones. This is one of the significant characteristics of the proposed method. The nonsingularity is proved analytically. The convergence of the proposed method is at least equal to that of the subspace iteration method with shift, and the operation counts of above two methods are almost the same when a large number of eigenpairs are required. To show the effectiveness of the proposed method, two numerical examples are considered.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2002.11a
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• pp.468-478
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• 2002

고품질의 영상 압축기인 JPEG2000의 기본 압축 코덱인 EBCOT(Embedded Block Coding With Optimized Truncation)를 설계하였다. 영상 압축기에서 Context 추출 구현을 위하여 코드블록(Code block)으로 분할하고, 비트플랜(Bit-Plane)코딩을 했으며, 3가지 패스 그룹으로 분리한 후 ZC, RLC, MR, SC를 하였다. 산술부호화는 덧셈 연산과 쉬프트 연산만을 사용하는 MQ-coder를 사용하였으며, Context들의 누적 확률을 추정하여 테이블을 작성하였고, 압축데이터를 산출하였다. 영상 압축을 위한 엔트로피 코더의 하드웨어 구현은 VHDL를 이용하여 설계를 하고, Synopsys사의 논리 회로 합성 도구를 사용하여 합성을 하였으며, Altera사의 FLEX 10K250 Device를 이용하여 FPGA로 구현하였다.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.11a
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• pp.468-478
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• 2002

고품질의 영상 압축기인 JPEG2000의 기본 압축 코덱인 EBCOT(Embedded Block Coding With Optimized Truncation)를 설계하였다. 영상 압축기에서 Context 추출 구현을 위하여 코드블록(Code block)으로 분할하고, 비트플랜(Bit-Plane)코딩을 했으며, 3가지 패스 그룹으로 분리한 후 ZC, RLC, MR, SC를 하였다. 산술부호화는 덧셈 연산과 쉬프트 연산만을 사용하는 MQ-coder를 사용하였으며, Context들의 누적 확률을 추정하여 테이블을 작성하였고, 압축데이터를 산출하였다. 영상 압축을 위한 엔트로피 코더의 하드웨어 구현은 VHDL를 이용하여 설계를 하고, Synopsys사의 논리 회로 합성 도구를 사용하여 합성을 하였으며, Altera사의 FLEX 10K250 Device를 이용하여 FPGA로 구현하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.10b
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• pp.911-914
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• 2000

본 논문에서는 화상을 정방블록으로 분할하여, 블록의 휘도 평균값으로부터 교류성분을 예측하는 정수 연산 알고리즘을 검토한다. 본 방식은 정수의 가감산과 비트 쉬프트 조작만으로 실현되고, 종래 방식과 비교하여 예측성능의 열화 없이 계산단가를 대폭으로 저감시킬 수 있다.

• Journal of Korea Multimedia Society
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• v.14 no.6
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• pp.759-765
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• 2011

In this paper, we proposed fast stream cipher MS64 for use mobile that it is secure, fast, and easy to implement software. The proposed algorithm use the fast operating 213-bit arithmetic shift register(ASR) to generate a binary sequence and produce 64-bit stream cipher by using simple logical operation in non linear transform. MS64 supports 128-bit key in encryption algorithm and satisfy with the safety requirement in modern encryption algorithm. In simulation result shows that MS64 is faster than a 32-bit stream cipher SSC2 in the speed of operation with small usage of memory thus MS64 can be used for mobile devices with fast ciphering.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1451-1459
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• 2004

In this paper, a low-power 32-point IMDCT structure is proposed for MP3. Through re-odering of IMDCT matrices, we propose the systolic structure operating with 16, 8, 4, 2, and 1 cycle, respectively. To reduce power consumption, multiplication of each sub blocks are implemented by add and shift operation with CSD(Canrmic sigled digit) form coefficients. To reduce, furthermore, the number of adders, we utilize the common sub-expression sharing techniques. With these techniques, the relative power consumption of the proposed structure is reduced by 58.4% comparison to the conventional structure using only 2's complement form coefficient. Validity of the proposed structure is proved through Verilog-HDL coding.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.158-160
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• 2016

전자서명(ECDSA), 키 교환(ECDH) 등에 사용되는 233-비트 타원곡선 암호(Elliptic Curve Cryptography; ECC) 프로세서의 설계에 대해 기술한다. $GF(2^{333})$ 상의 덧셈, 곱셈, 나눗셈 등의 유한체 연산을 지원하며, 하드웨어 자원 소모가 적은 쉬프트 연산과 XOR 연산만을 이용하여 구현하였다. 스칼라 곱셈은 modified montgomery ladder 알고리듬을 이용하여 구현하였으며, 정수 k의 정보를 노출하지 않고, 단순 전력분석에 보다 안전하다. 스칼라 곱셈 연산은 최대 490,699 클록 사이클이 소요된다. 설계된 ECC 프로세서는 Xilinx ISim을 이용한 시뮬레이션 결과값과 한국인터넷진흥원(KISA)의 참조 구현 값을 비교하여 정상 동작함을 확인하였다. Xilinx Virtex5 XC5VSX95T FPGA 디바이스 합성결과 1,576 슬라이스로 구현되었으며, 189 MHz의 최대 동작주파수를 갖는다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.773-778
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• 1993

A new approach is proposed for the DCT which is widely utilized in the image processing, The approach replaces mutiplications with shift and additions, In the image restored by the proposed DCT and IDCT, no visible degration is observed and PSNR(Peak to Peak Signal to Noise Ratio) is greater than 35 dB for all cases, proving the usefulness of the proposal.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.765-770
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• 2012

In this paper, we proposed an effective hardware structure using DCT-based inra-prediction mode selection to reduce computational complexity caused by intra mode decision. In this hardware structure, the input block is transformed at first and then analyzed to determine its texture directional tendency. the complexity has solved by performing intra prediction in only predicted edge direction. $4{\times}4$ DCT is calculated in one cycle using Multitransform_PE and Inta_pred_PE calculates one prediction mode in two cycles. Experimental results show that the proposed Intra prediction encoding needs only 517 cycles for one macroblock encoding. This architecture improves the performance by about 17% than previous designs. For hardware implementation, the proposed intra prediction encoder is implemented using Verilog HDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis results show that the proposed architecture can run at 125MHz.