• Proceedings of the Korea Information Processing Society Conference
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• 2016.04a
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• pp.536-538
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• 2016

최근 소프트웨어가 사회에서 하는 일이 점점 더 증가함에 따라 소프트웨어의 개발비용도 함께 증가하고 있다. 소프트웨어의 개발비용 중 에러를 찾아내는 소프트웨어 테스팅이 상당한 부분을 차지하고 있는데 테스팅에 소요되는 비용 때문에 테스팅을 등한시 하는 경우가 많다. 그럼에도 불구하고 소프트웨어의 기능 추가나 변경이 이루어질 때마다 테스트를 진행하여야 소프트웨어의 에러를 최소화할 수 있다. 하지만 개발이 진행될수록 소요되는 비용이 증가하는 경우가 많아 실제 소프트웨어 개발에선 개발 기한이 다가올수록 회귀 테스트를 기피하게 된다. 본 논문에서는 이러한 문제를 해결하기 위해 소프트웨어의 개발을 진행하면서 형상관리를 통해 소프트웨어의 변경이 있을 때마다 회귀 테스트를 자동으로 수행해주는 도구를 제안한다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.35-41
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• 2012

Due to the technology scaling, more transistors can be placed on a cache memories of a processor. However, processors become more vulnerable to the soft error because of the highly integrated transistors, and consequently, the reliability of the cache memory must consider seriously at the design space level. In this paper, we propose the reliability improving technique which can be achieved with low energy and low area overheads. The simulation experiments of the proposed scheme shows over 95.4% of protection rate against the soft error with only 0.26% of performance degradations. Also, It requires only 2.96% of extra energy consumption.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.3
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• pp.111-116
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• 2013

With technology scaling, soft error rate has greatly increased in embedded systems. Due to high performance and low power consumption, VLIW (Very Long Instruction Word) architectures have been widely used in embedded systems and thus many researches have been studied to improve the reliability of a system by duplicating instructions in VLIW architectures. However, existing studies have ignored the feature, called VLES (Variable Length Execution Set), which is adopted in most modern VLIW architectures to reduce code size. In this paper, we propose how to support instruction duplication in VLIW architecture with VLES. Our experimental results demonstrate that a VLIW architecture with VLES shows 64% code size decrement on average at the cost of about 4% additional cell area as compared to the case of a VLIW architecture without VLES when instruction duplication is applied to both architectures. Also, it is shown that the case with VLES does not cause extra execution time compared to the case without VLES.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.9-10
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• 2011

임베디드 시스템에서 저전력 공급, 칩사이즈 축소, 낮은 노이즈 마진 등 설계기법이 날로 향상됨에 따라 소프트에러가 기하급수적으로 늘어나고 있다. 본 논문에서는 VLIW 아키텍처에서 치명적인 오류를 일으키는 이런 소프트에러들을 검출하고 수정하는 기법을 제안하고자 한다.

• 한국항공운항학회:학술대회논문집
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• 2015.11a
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• pp.252-256
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• 2015

항공기 운항과 밀접하게 관련되는 장비중에 하나가 CNS&ATM관련 탑재 항공전자 장비이다. 임베디드 소프트웨어가 들어간 항전장비 개발에 에러 유입이 주로 요구도 분석 및 아키텍쳐 설계에서 일어난다. 항공전자 장비 개발에 운영자가 적극적으로 참여함으로써 에러 발생 요인 감소, 고장 영향성 분석, 요구도 기반 시험 등을 효율적으로 수행할 수가 있어, 장비의 개발기간 및 비용을 줄일 수가 있다.

• Journal of IKEEE
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• v.27 no.4
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• pp.683-686
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• 2023

In this paper, we designed a Delayed Dual Core Lock-Step (D-DCLS) processor where two cores operate same instructions with delay and the result is compared to mitigate soft errors and common mode failures in automotive electronic systems. Because D-DCLS does not know which core an error occurred in, each core must be recovered to the point before the error occurred, but complex hardware modifications are required to return all intermediate values on the pipeline stage. In this paper, in order for easy hardware implementation, all register values are saved to a buffer whenever a branch instruction is executed. When an error is detected, the saved register values are automatically restored, and then 'BX LR' instruction is executed to return to the last branch point. The proposed D-DCLS processor was designed using Verilog HDL and was confirmed to continue normal operation after automatically recovering error.

• Journal of the Korea Computer Industry Society
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• v.4 no.4
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• pp.553-560
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• 2003

Can presume number of software failure or remaining fault that is expected with test data that is collected by decided time using SRGM that is studied until present. Therefore, can forecast software reliability achievement degree and software reliability use step. But, reliability evaluation according to if choose any model can change. Therefore, we present SRGM that consider test cost to error detection and error delete cost as SRGM that consider error delete cost in this research. Using this SRGM, can presume number of remaining fault in software, reliability and optimal release time.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.11a
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• pp.383-386
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• 2007

X-Forms 기반의 웹 UI(User Interface)를 개발하는 소프트웨어는 개발이 완료되어 운영되는 과정에도 사용자의요구, 성능향상, 기능개선, 기능추가 등의 이유로 변경이 가능하다. 이러한 소프트웨어의 유지보수도 일반적인 요구사항명세, 분석, 설계, 구현의 개발 프로세스를 따른다. 본 논문에서는 UI 개발 소프트웨어의 유지보수 단계에서 효율적인 테스트를 하기 위해 V-모델을 확장, 변형한 테스트 프로세스 제안한다. 제안한 테스트 프로세스의 주요 활동은 요구사항분석을 통한 테스트 계획, 테스트 데이터를 식별하고 환경을 구축하는 분석과 설계, 테스트 케이스를 명세화하고 테스팅 방법론을 적용하는 구현과 실현, 리포팅과 산출물을 정리하는 테스트 마감 활동으로 진행한다. 웹 UI 개발 소프트웨어의 특징에 맡게 테스트 프로세스를 구축하고 실무에 적용하여 에러 검출률, 테스트 시간, 테스트 결과의 효율성을 높일 수 있는 방법을 제안한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.15-23
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• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.1
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• pp.59-66
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• 2000

As the highly complex and precise control functions are required in modern industrial process control system, the complex function models and developed in each hardware and software of PLC. The SFC graphical language is very powerful for describing the sequential logic control algorithm, on the other hand it graphical language is very powerful for describing the sequential logic control algorithm, on the other hand it has problems in describing the interlock logic control algorithm, such as error management algorithm. In this paper, we propose the efficient error management method using the action qualifiers to design the error management algorithm in industrial process control system described scheme, we realize the error management logic in process control system of film coating machine.From the experiment results, we confirm that the proposed scheme is very useful in aspects to realize easily th error management logic and to reduce the memory capacity for user's program.