• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.1-1
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• 2001

DRAM에서 셀 캐패시터의 누설 전류 영향을 고려하여 소프트 에러율을 예측하였다. DRAM의 동작 과정에서 누설 전류의 영향으로 셀 캐패시터는 전하량이 감소하고, 이에 따른 소프트 에러율을 DRAM의 각 동작 모드에 대하여 계산하였다. 누설 전류가 작을 경우에는 /bit mode가 소프트 에러에 취약했지만, 누설전류가 커질수록 memory 모드가 소프트 에러에 가장 취약함을 보였다. 실제 256M급 DRAM의 구조에 적용하여, 셀 캐패시턴스, bit line 캐패시턴스, sense amplifier의 입력 전압 감도들이 변화할 때 소프트 에러에 미치는 영향을 예측하였고, 이 결과들은 차세대 DARM 연구의 최적 셀 설계에 이용될 수 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.677-680
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• 2011

Error detection and correcting codes are typically used to protect against soft errors. In addition, scrubbing is applied which is a fundamental technique to avoid the accumulation of soft errors. This paper introduces an optimal scrubbing scheme, which is suitable for a system with auto error detection and correction logic. An auto error detection and correction logic can correct soft errors without CPU's writing operation. The proposed scrubbing scheme leads to maximum reliability by considering both allowable scrubbing load and the periodic accesses to memory by the tasks running in the system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.655-658
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• 2016

Xilinx 7-Series FPGA(Field Programmable Gate Array)s mainly used for the implementation of high-performance digital circuit have SRAM-type configuration memory and can malfunction when soft errors occur in their configuration memory. SEM(Soft Error Mitigation Controller) offered by Xilinx helps users mitigate the influence of soft errors in configuration memory. When soft errors occur, SEM Controller can recover the state of FPGA through partial reconfiguration if the soft errors are correctable by ECC(Error Correction Code) and CRC(Cyclic Redundancy Code). This paper presents the availability analysis of Xilinx 7-Series FPGAs against soft errors under the protection of the SEM Controller. Availability functions are derived and compared according to the correction capability of the SEM Controller. The result may help to estimate the reliability of SRAM-based FPGA running in an environment where soft errors may occur.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.87-94
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• 2001

A soft error rate for DRAM was predicted in connection with the leakage current in cell capacitor. The charge in cell capacitor was decreased during the DRAM operation, and soft error retes due to the leakage current were calculated in various operation mode of DRAM. It was found that the soft error rate of the /bit mode was dominant with small leakage current, but as increasing the leakage current memory mode shown the dominant effect on soft error rate. Using the 256M grade DRAM structure it was predicted that the soft error rate was influenced by the change of the cell capacitance, bit line capacitance, and the input voltage sensitivity of sense amplifier, and these results can be used to the design of the optimum cells in the next generation DRAM development.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.701-704
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• 2011

The reliability of a computer system largely depends on that of its memory systems, which are vulnerable to soft errors. Soft errors can be coped with a combination of an Error Detection & Correction circuit and scrubbing operation. Smaller geometries and lower voltage of advanced memories makes them more prone to suffer multibit soft errors. A memory structure against multibit soft errors and a suitable scrubbing scheme for it were proposed. This paper introduces a key issue for the scrubbing of the memories with protection against multibit soft errors and the result of the performance analysis from a reliability point of view.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.55-61
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• 1999

A soft error rate (SER) simulator for DRAM was developed. In comparison to the other SER simulator using device simulator or Monte Carlo simulator, the proposed simulator substantially reduced the CPU time using an analytical model for the alpha-particle-induced charge collection. By analysing the soft error modes in DRAM, the bit-bar mode was identified as the main cause of soft error. Using the new SER simulator, SER of 256M DRAM was investigated and it was found that the storage capacitance had a 5fF margin.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.5
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• pp.430-437
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• 2021

In this paper, we propose a robust face recognition method against soft errors with a deep convolutional generative adversarial network(DCGAN) based compensation method by a cross-layer approach. When soft-errors occur in block data of JPEG files, these blocks can be decoded inappropriately. In previous results, these blocks have been replaced using a mean face, thereby improving recognition ratio to a certain degree. This paper uses a DCGAN-based compensation approach to extend the previous results. When soft errors are detected in an embedded system layer using parity bit checkers, they are compensated in the application layer using compensated block data by a DCGAN-based compensation method. Regarding soft errors and block data loss in facial images, a DCGAN architecture is redesigned to compensate for the block data loss. Simulation results show that the proposed method effectively compensates for performance degradation due to soft errors.

• Journal of the Korea Society of Computer and Information
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• v.29 no.6
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• pp.89-100
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• 2024

The primary goal of software testing is to identify and correct errors within software. A key challenge in this process is error masking, where errors disappear internally before reaching the output. This paper investigates the causes and characteristics of error masking, which complicates software testing. The study involved injecting artificial errors into three software programs to examine the extent of error masking by various test cases and to explore the underlying reasons. The experiment yielded four major findings. First, about 50% of the error masking occurred because the errors were not executed. Second, among various operators, logical and arithmetic operators masked errors less frequently, while relational and temporal operators tended to mask errors more extensively. Third, certain test cases demonstrated exceptional effectiveness in propagating errors to the output. Fourth, the type of error injected influenced the masking effect.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10a
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• pp.569-571
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• 1999

소프트웨어의 신뢰도는 하드웨어의 신뢰도와 고장메타니즘이 다르므로 하드웨어의 신뢰도 모델을 그대로 이용할 수 없다. 소프트웨어의 신뢰도를 추정하기 위한 방법은 그동안 Jelinski-Moranda(JM) 모델을 비롯하여 많은 기법이 연구되었다. 그러나, 아직까지 만족하다고 인정할 만한 신뢰도모델링은 개발되지 않았다. 본 연구에서는 소프트웨어의 테스트를 통하여 검출되는 에러 개수의 추세를 가지고 비제차포아송과정(NHPP)의 파라미터를 찾아 신뢰도함수를 구하고자 하며, 아울러, 테스트중단시간을 결정하고자 한다. 파라미터를 찾는 방법은 maximum likelihood estimate(MLE) 기법을 이용하며, 테스트 중단시간은 구해진 파라미터를 신뢰도 함수에 대입하여 결정한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.601-606
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• 2017

SRAM-based FPGAs mainly used to develop and implement high-performance circuits have SRAM-type configuration memory. Soft errors in memory devices are the main threat from a reliability point of view. Soft errors occurring in the configuration memory of FPGAs cause FPGAs to malfunction. SEM(Soft Error Mitigation) Controllers offered by Xilinx can mitigate the influence of soft errors in configuration memory. SEM Controllers use ECC(Error Correction Code) and CRC(Cyclic Redundancy Code) which are placed around the configuration memory to detect and correct the errors. The correction is done through a partial reconfiguration process. This paper presents the availability analysis of SRAM-based FPGAs against soft errors under the protection of SEM Controllers. Availability functions were derived and compared according to the correction capability of SEM Controllers of several different families of FPGAs. The result may help select an SRAM-based FPGA part and estimate the availability of FPGAs running in an environment where soft errors occur.