• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2017.04a
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• pp.159-159
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• 2017

스마트 시설환경은 대표적으로 원예, 축산 분야 등 여러 형태의 농업현장에 정보 통신 및 데이터 분석 기술을 도입하고 있는 시설화된 생산 환경이라 할 수 있다. 근래에 하드웨어적으로 급증한 스마트 시설환경에서 생산되는 방대한 생육/환경 데이터를 올바르고 적합하게 사용하기 위해서는 일반 산업 현장과는 차별화 된 분석기법이 요구된다고 할 수 있다. 소프트웨어 공학 분야에서 연구된 빅데이터 처리 기술을 기계적으로 농업 분야의 빅데이터에 적용하기에는 한계가 있을 수 있다. 시설환경 내/외부의 다양한 환경 변수는 시계열 데이터의 난해성, 비가역성, 불특정성, 비정형 패턴 등에 기인하여 예측 모델 연구가 매우 난해한 대상이기 때문이라 할 수 있다. 본 연구에서는 근래에 관심이 급증하고 있는 인공신경망 연구 소프트웨어인 Tensorflow (www.tensorflow.org)와 대표적인 Open source인 OpenNN (www.openn.net)을 스마트 시설환경 환경변수 상호간 상관성 분석에 응용하였다. 해당 소프트웨어 라이브러리의 운영환경을 살펴보면 Tensorflow 는 Linux(Ubuntu 16.04.4), Max OS X(EL capitan 10.11), Windows (x86 compatible)에서 활용가능하고, OpenNN은 별도의 운영환경에 대한 바이너리를 제공하지 않고 소스코드 전체를 제공하므로, 해당 운영환경에서 바이너리 컴파일 후 활용이 가능하다. 소프트웨어 개발 언어의 경우 Tensorflow는 python이 기본 언어이며 python(v2.7 or v3.N) 가상 환경 내에서 개발이 수행이 된다. 주의 깊게 살펴볼 부분은 이러한 개발 환경의 제약으로 인하여 Tensorflow의 주요한 장점 중에 하나인 고속 연산 기능 수행이 일부 운영 환경에 국한이 되어 제공이 된다는 점이다. GPU(Graphics Processing Unit)의 제공하는 하드웨어 가속기능은 Linux 운영체제에서 활용이 가능하다. 가상 개발 환경에 운영되는 한계로 인하여 실시간 정보 처리에는 한계가 따르므로 이에 대한 고려가 필요하다. 한편 근래(2017.03)에 공개된 Tensorflow API r1.0의 경우 python, C++, Java언어와 함께 Go라는 언어를 새로 지원하여 개발자의 활용 범위를 매우 높였다. OpenNN의 경우 C++ 언어를 기본으로 제공하며 C++ 컴파일러를 지원하는 임의의 개발 환경에서 모두 활용이 가능하다. 특징은 클러스터링 플랫폼과 연동을 통해 하드웨어 가속 기능의 부재를 일부 극복했다는 점이다. 상기 두 가지 패키지를 이용하여 2016년 2월부터 5월 까지 충북 음성군 소재 딸기 온실 내부에서 취득한 온도, 습도, 조도, CO2에 대하여 Large-scale linear model을 실험적(시간단위, 일단위, 주단위 분할)으로 적용하고, 인접한 세그먼트의 환경변수 예측 모델링을 수행하였다. 동일한 조건의 학습을 수행함에 있어, Tensorflow가 개발 소요 시간과 학습 실행 속도 측면에서 매우 우세하였다. OpenNN을 이용하여 대등한 성능을 보이기 위해선 병렬 클러스터링 기술을 활용해야 할 것이다. 오프라인 일괄(Offline batch)처리 방식의 한계가 있는 인공신경망 모델링 기법과 현장 보급이 불가능한 고성능 하드웨어 연산 장치에 대한 대안 마련을 위한 연구가 필요하다.

• Journal of Korea Multimedia Society
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• v.13 no.11
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• pp.1575-1585
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• 2010

It is very important to forecast a back resource of a software development effort at the early stage of development life cycle for successful project processing, and it is carried out through software size estimation. The recent trend of software size estimation method is focused on the user's value such as FPA. We measure the actual development effort through case study and calculate CFP directly according to the cosmic-ffp manual V.3.0. in this paper. We also propose the software development effort estimation model by using the produced data. COSMIC-FFP does not use weights of necessary function elements, and so it has disadvantage in estimating sizes. This paper proposes the estimation model to estimate the precision software size by using system complexity as weight.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10c
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• pp.145-147
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• 2003

홈 제어 네트워크는 전력선으로 대표되는 물리적 네트워크를 기반으로 저속의 신뢰도 있는 통신을 한다. 현재 홈 제어 네트워크의 표준으로 거론되고 있는 것들은 CEBUS, EIB, LonWorks 등이 있다. 본 논문에서는 ETRI에서 작년에 개발한 론웍스(LonWorks) 시스템을 구성 관리하는 서버 소프트웨어인 LonWare(version 2.0)의 다중 바인딩을 지원하기 위한 연결(Connections) 구조를 제안한다. Echelon사에서 제안하는 LonWorks 시스템의 구성관리 도구로서의 LonMaker는 자체적으로 개발한 LNS (LonWorks Network Service)라고 하는 비 표준화된 구성 관리 기술을 통해서 네트워크를 관리하도록 지원하며, 상기한 LNS를 인프라로 활용하는 도구로서, LNS는 빌딩 혹은 가정 내에 LonWorks 네트워크로 연결되어 있는 디바이스들에 대한 정보를 DB화하여 구축된 자료를 기반 으로 디바이스들간에 연동이 가능하도록 지원한다. 그러나 고가이며, 바인딩 과정 시 론웍스 네트워크 상에 필요 이상의 패킷을 발생시켜 전력선 채널의 Bandwidth를 감소시키며, 또한 바이딩 과정을 마치는데 걸리는 시간을 증가시킨다. 이에 본 논문에서는 다중 바이딩을 지원하는 홈 네트워크 구성 관리 서버 소프트웨어의 연결 구조를 통해서 LonWare v2.0의 유니캐스트(unicast) 바이딩시 발생 했던 모든 문제를 제거하고, 바인딩에 필요한 패킷을 최적화 하여 바인딩에 걸리는 시간을 단축시키며, 성능의 주요한 요소인 디바이스의 리소스를 최소화하는 방법으로 접근하여 바인딩 시 처리능력의 한계를 가지고 있는 뉴런칩 기반의 론웍스 디바이스의 시스템 사양에 영향을 주지 않도록 제안하였다. 제안된 리눅스 기반의 홈 네트워크 구성 관리 소프트웨어의 다중 바인딩 기능을 통해 론웍스 네트워크상의 다양한 디바이스들간의 네트워크 다양화와 분산화 기능을 얻을 수 있었고, 기존의 고가의 해외 솔루션인 Echelon사의 LonMaker 소프트웨어를 사용하지 않고도 국내의 순수 솔루션인 리눅스 기반의 LonWare 3.0 다중 바인딩 기능을 통해 저 비용으로 홈 네트워크 구성 관리 서버 시스템 개발에 대한 비용을 줄일 수 있다.

• The KIPS Transactions:PartD
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• v.14D no.7
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• pp.773-782
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• 2007

Software produce line engineering is a method that prepares for future reuse and supports seamless reuse in the application development process. Analyzing the commonality and variability between products in a product line is one of the essential concerns that must be considered when building a product line. In this paper, we suggest to combine a product line engineering approach with RFID applications technology. More concretely, common activities are identified among the RFID-enable applications and the variability in the common activities is analyzed in detail. Then, we suggest reusable product line architecture as a product line asset. In addition, as a tool for supporting this research, a framework which provides both reusable product line architecture for REID applications and the components that implement concrete realization of the architecture is developed. Sharing a common architecture and reusing assets to deploy recurrent services may be considered an advantage in terms of economic significance and overall quality.

• Progress in Medical Physics
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• v.26 no.1
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• pp.18-27
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• 2015

Since a Compton camera has high detection sensitivity due to electronic collimation and a good energy resolution, it is a potential imaging system for nuclear medicine. In this study, we investigated the feasibility of a Compton camera for multi-tracer imaging and proposed a rotating Compton camera to satisfy Orlov's condition for 3D imaging. Two software phantoms of 140 and 511 keV radiation sources were used for Monte-Carlo simulation and then the simulation data were reconstructed by listmode ordered subset expectation maximization to evaluate the capability of multi-tracer imaging in a Compton camera. And the Compton camera rotating around the object was proposed and tested with different rotation angle steps for improving the limited coverage of the fixed conventional Compton camera over the field-of-view in terms of histogram of angles in spherical coordinates. The simulation data showed the separate 140 and 511 keV images from simultaneous multi-tracer detection in both 2D and 3D imaging and the number of valid projection lines on the conical surfaces was inversely proportional to the decrease of rotation angle. Considering computation load and proper number of projection lines on the conical surface, the rotation angle of 30 degree was sufficient for 3D imaging of the Compton camera in terms of 26 min of computation time and 5 million of detected event number and the increased detection time can be solved with multiple Compton camera system. The Compton camera proposed in this study can be effective system for multi-tracer imaging and is a potential system for development of various disease diagnosis and therapy approaches.

• KIPS Transactions on Software and Data Engineering
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• v.9 no.5
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• pp.169-176
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• 2020

Recently, deep neural networks (DNNs) have brought revolutions to many mobile and embedded devices by providing human-level machine intelligence for various applications. However, high inference accuracy of such DNNs comes at high computational costs, and, hence, there have been significant efforts to reduce computational overheads of DNNs either by compressing off-the-shelf models or by designing a new small footprint DNN architecture tailored to resource constrained devices. One notable recent paradigm in designing small footprint DNN models is sharing parameters in several layers. However, in previous approaches, the parameter-sharing techniques have been applied to large deep networks, such as ResNet, that are known to have high redundancy. In this paper, we propose a parameter-sharing method for already parameter-efficient small networks such as ShuffleNetV2. In our approach, small templates are combined with small layer-specific parameters to generate weights. Our experiment results on ImageNet and CIFAR100 datasets show that our approach can reduce the size of parameters by 15%-35% of ShuffleNetV2 while achieving smaller drops in accuracies compared to previous parameter-sharing and pruning approaches. We further show that the proposed approach is efficient in terms of latency and energy consumption on modern embedded devices.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.2
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• pp.15-26
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• 2021

Recently, as the introduction of cloud, mobile, and IoT has become active, there is a growing need for technology development that can supplement the limitations of traditional security solutions based on fixed perimeters such as firewalls and Network Access Control (NAC). In response to this, SDP (Software Defined Perimeter) has recently emerged as a new base technology. Unlike existing security technologies, SDP can sets security boundaries (install Gateway S/W) regardless of the location of the protected resources (servers, IoT gateways, etc.) and neutralize most of the network-based hacking attacks that are becoming increasingly sofiscated. In particular, SDP is regarded as a security technology suitable for the cloud and IoT fields. In this study, a new access control system was proposed by combining SDP and hash tree-based large-scale data high-speed signature technology. Through the process authentication function using large-scale data high-speed signature technology, it prevents the threat of unknown malware intruding into the endpoint in advance, and implements a kernel-level security technology that makes it impossible for user-level attacks during the backup and recovery of major data. As a result, endpoint security, which is a weak part of SDP, has been strengthened. The proposed system was developed as a prototype, and the performance test was completed through a test of an authorized testing agency (TTA V&V Test). The SDP-based access control solution is a technology with high potential that can be used in smart car security.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.

• Journal of the Institute of Convergence Signal Processing
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• v.19 no.4
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• pp.153-161
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• 2018

This paper describes the performance improvement of Software (SW) digital filter using GPU (Graphical Processing Unit). The previous developed SW digital filter has a problem that it operates on a CPU (Central Processing Unit) basis and has a slow speed. The GPU was introduced to filter the data of the EAVN (East Asian VLBI Network) observation to improve the operation speed and to process data with other stations through filtering, respectively. In order to enhance the computational speed of the SW digital filter, NVIDIA Titan V GPU board with built-in Tensor Core is used. The processing speed of about 0.78 (1Gbps, 16MHz BW, 16-IF) and 1.1 (2Gbps, 32MHz BW, 16-IF) times for the observing time was achieved by filtering the 95 second observation data of 2 Gbps (512 MHz BW, 1-IF), respectively. In addition, 2Gbps data is digitally filtered for the 1 and 2Gbps simultaneously observed with KVN (Korean VLBI Network), and compared with the 1Gbps, we obtained similar values such as cross power spectrum, phase, and SNR (Signal to Noise Ratio). As a result, the effectiveness of developed SW digital filter using GPU in this research was confirmed for utilizing the data processing and analysis. In the future, it is expected that the observation data will be able to be filtered in real time when the distributed processing optimization of source code for using multiple GPU boards.

• Journal of KIISE:Software and Applications
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• v.32 no.3
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• pp.163-172
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• 2005

Product Line Engineering (PLE) has been widely accepted as a representative software reuse methodology by using core assets. Product line architecture (PLA) is a key element of core assets. However, current research works on designing PLA do not provide sufficient and detailed guidelines of defining PLA and reflecting variability in the architecture. In this paper, we present a reference model of PLA and propose a process to design PLA with detailed instructions. Especially architectural variability is codified by describing decision model depending variation points and traced through PLA activities. The proposed process would make it feasible to apply PLE to practice areas.