• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.50-58
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• 2013

In this paper, we present the implementation result of an UWB terminal for mobile tactical networks. Considering the major characteristics of the terminals of tactical networks, i) targeting voice service, ii) pedestrian users, and iii) demanding high network fidelity, we designed all protocol layers from physical layer to applications layer. The designed terminal is implemented in forms of software and hardware with RF ASIC, FPGA, DSP, and GPP. The functionality of the implemented terminal is validated by successfully performing 1 to 1 and multi-hop voice communication test.

• KIPS Transactions on Software and Data Engineering
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• v.3 no.9
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• pp.381-388
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• 2014

In this paper, we deal with implementation issues of an unknown word classifier for middle-school level English writing test. We define the type of unknown words occurred in English text and discuss the detection process for unknown words. Also, we define the type of swear words occurred in students's English writings, and suggest how to handle this type of words. We implement an unknown word classifier with a swear detection module for developing an automatic English writing scoring system. By experiments with actual test data, we evaluate the accuracy of the unknown word classifier as well as the swear detection module.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.11a
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• pp.395-398
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• 2007

오늘날 기업에서의 IT 는 급격한 비즈니스 환경의 변화와 다양한 비즈니스 모델의 출현으로 인해 점점 더 복잡해지고 있고, 비즈니스의 IT 의존도 또한 지속적으로 증가하고 있다. 이러한 상황에서 기업의 정보시스템을 운영하는 IT 운영조직은 사용자에게 IT 서비스의 품질향상과 비즈니스의 연속성을 보장할 수 있는 지원체계를 필요로 하고 있다. 1990년대 후반에 들어서 ITIL 을 기반으로 한 ITSM 개념이 국내에 도입 되면서 기존의 콜센터와 헬프데스크를 통한 IT 서비스지원 방식을 서비스데스크로 통합하게 되었고, 서비스데스크 자동화 시스템의 도입을 통해 기업의 모든 비즈니스 조직의 IT 와 관련된 요구사항을 관리하고 있다. 하지만 이러한 서비스데스크 자동화 시스템은 IT 서비스 제공자 관점에서 구축되었고 운영방향 또한 어플리케이션, 서버, 네트워크 등 기술적인 구성요소의 성능 향상에만 초점을 두었기 때문에 현업 사용자들이 만족 할 수 있는 실질적인 수준의 서비스 개선은 이루어지지 못하고 있다. 이에 본 연구에서는 고객관점에서의 요구사항 분석을 통해, 운영조직의 IT 서비스 요청에 대한 처리활동을 단순처리와 일반처리로 분류하고 이를 자동화 시스템에 반영 하였고, 실제 A 사(社)의 IT 운영조직에 적용하여, 비효율적인 저부가가치 활동과 고부가 가치의 활동이 시스템을 통해 분류가 가능함을 보였다. 아울러 IT 운영조직의 활동을 정량적으로 관리 할 수 있도록 관리지표를 발굴하고 자동화 시스템의 서비스요청관리 프로세스에 적용하여 IT 서비스를 제공받는 회사의 관리조직과 경영층이 IT 운영조직의 활동을 정량적으로 관리하고 측정할 수 있는 IT 서비스데스크 자동화 시스템의 개선모델을 제시 하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.239-245
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• 2019

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. In this paper, according to the emergence of RISC-V architecture, we describe the RISC-V processor instruction set constituted by arithmetic logic, memory, branch, control, status register, environment call and break point instructions. Using ModelSim and Quartus-II, 38 instructions of RISC-V has been successfully simulated and synthesized.

• KIPS Transactions on Software and Data Engineering
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• v.10 no.8
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• pp.319-330
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• 2021

Recently, in the field of open domain natural language question answering, multi-task, multi-hop question answering has been studied extensively. In this paper, we propose a novel deep neural network model using hierarchical graphs to answer effectively such multi-task, multi-hop questions. The proposed model extracts different levels of contextual information from multiple paragraphs using hierarchical graphs and graph neural networks, and then utilize them to predict answer type, supporting sentences and answer spans simultaneously. Conducting experiments with the HotpotQA benchmark dataset, we show high performance and positive effects of the proposed model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.7-14
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• 2009

Lately, NAND flash cards have been used to store massive amounts of multimedia data. However, these nand flash cells itself has a slow operation time and by that, the nand flash cards are not appropriate for high performance massive data transfer. Indeed, most flash card products have a disadvantage in that they require plenty of time to transfer massive amounts of data. Therefore, we propose a new architectural design for the hardware and software of the NAND flash cards by improving their data transfer rate. Our design is based on a multiprocessing which is different from the conventional serial processing method. We simulated our design under the VIP (Virtual IP) environment, and verified our work using FPGA test platforms. As a result, the downloading performances was approximately 160MB/s on VIP and 85.3MB/s on FPGA.

• Journal of The Korean Association of Information Education
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• v.9 no.3
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• pp.483-500
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• 2005

The purpose of the study was to explore the conceptual and theoretical fundamentals of learning object. Learning object, a new paradigm for instructional design in the era of information technology, has attracted much research efforts since it has lots of advantages in terms of production efficiency and use effectiveness. A theory for the systematic design of this new instructional design, however, looks far from mature. Since the birth of the idea of a learning object has been found in the field of computer software design, such as object-oriented software development, learning object does not have enough theoretical underpinnings in terms of learning and instruction. The researcher tried to establish theoretical foundations for this new, alien concept as a learning design theory. Relevant research efforts and discourses have been discussed for this purpose.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.44-59
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• 2006

This paper describes the efficient implementation of DNA sequence generate system with genetic algorithm for reducing computation time of NACST. The proposed processor is based on genetic algerian with fitness functions which would suit the point of reference for generated sequences. In order to implement efficient hardware structure, we used the pipelined structure. In addition our design was applied the parallelism to achieve even better simulation time than the sequence generator system which is designed on software. In this paper, our hardware is implemented on the FPGA board with xc2v6000 devices. Through experiment, the proposed hardware achieves 467 times speed-up over software on a PC and sequence generate performance of hardware is same with software.

• Journal of Broadcast Engineering
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• v.21 no.3
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• pp.341-348
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• 2016

HEVC is the next compression standard and is expected to be used widely replacing the conventional H.264/AVC standard. The compression ratio of the HEVC is twice times than H.264/AVC, whereas its computational complexity is increased by up to 40%. Many research efforts have been made to reduce the computational complexity and to speed up encoding. For intra coding, the rough mode decision (RMD) is commonly applied. The rate-distortion optimization (RDO) process to decide the best mode is too complex so that RMD chooses the candidate modes with a simple process and sends the candidates to RDO process. However, for large-size blocks, the RMD also requires considerable computations. In this paper, a down-sampling scheme is proposed for the RMD process. The reference pixel loading, predicted pixel generation are performed using the down-sampled pixel data. When the proposed scheme is applied to the RMD, the computational complexity is reduced by 70% with a marginal bitrate increase of 0.04%. In terms of area of hardware-based RMD, the gate count and the buffer size is reduced 33% and 66%, respectively.

• KIPS Transactions on Software and Data Engineering
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• v.4 no.1
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• pp.45-56
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• 2015

In this paper, we present a method that can detect context-sensitive word errors and generate correction candidates. Spelling error detection is one of the most widespread research topics, however, the approach proposed in this paper is adjusted for an automated English scoring system. A common strategy in context-sensitive word error detection is using a pre-defined confusion set to generate correction candidates. We automatically generate a confusion set in order to consider the characteristics of sentences written by second-language learners. We define a word error that cannot be detected by a conventional grammar checker because of part-of-speech ambiguity, and propose how to detect the error and generate correction candidates for this kind of error. An experiment is performed on the English writings composed by junior-high school students whose mother tongue is Korean. The f1 value of the proposed method is 70.48%, which shows that our method is promising comparing to the current-state-of-the art.