• Title/Summary/Keyword: 설계 오류

Search Result 1,322, Processing Time 0.032 seconds

Design of the Kernel Hardening Function for Stability the Linux Operating System (리눅스 운영체제 안정화를 위한 커널 하드닝 기능 설계)

  • Jang Seung-Ju
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.9 no.6
    • /
    • pp.1333-1340
    • /
    • 2005
  • This paper is based on the study to reduce a system panic state. A panic state could be caused by a programmer or an administrator's careless mistake. The proposed hardening Operating System of this paper stops the process which is running in the kernel with an error. The error process for the value type and the address type of a certain variable have to be restored. Installed with kernel hardening, Operating System checks the recovery possibility of the process first and then restores the process which can be recovered. When it is possible to recover the kernel code with an error, it is to be recovered in ASSERT() function.

A Study on the Misconceptions in the Self-directed Learning Using a Mathematics Digital Textbook: Focused on the Division of Fractions (수학과 디지털교과서 자기주도적 학습에서 나타난 오개념에 대한 연구: 분수의 나눈셈을 중심으로)

  • Heo, Hae-Ja;Choi, Jeong-Im
    • School Mathematics
    • /
    • v.11 no.4
    • /
    • pp.643-664
    • /
    • 2009
  • This study was aimed to understand the problems that students experience during the self--directed study of a mathematics digital textbook and to find the implications for the design of digital textbook. For this study, we analyzed the process of self-directed learning on 'division of fractions with same denominator' using digital textbook by eight 6th graders. Students asked to use think aloud method while they study the unit. Their learning process was videotaped and analyzed by researchers after the experiment. After the self-directed learning, students filled out a test items and participated interview with a researcher. The result showed that students experienced several misconceptions and errors while using a digital textbook. The types of misconceptions and errors were cataegorized as "misconceptions and errors caused by a mathematics textbook" and "misconceptions and errors caused by a digital textbook". Especially, students showed several important misconceptions and errors because of the design factors. This implies we need to consider the causes of misconceptions for the design of a digital textbook.

  • PDF

The Effects of Chatbot's Error Types and Structures of Error Message on User Experience (챗봇의 오류 유형과 오류 메시지 구조화 여부가 사용자 경험에 미치는 영향)

  • Lee, Mi-Jin;Han, Kwang-Hee
    • The Journal of the Korea Contents Association
    • /
    • v.21 no.6
    • /
    • pp.19-34
    • /
    • 2021
  • The aim of this study is verifying the effects of chatbot's error types and structures of error message on attitude, behavior intention towards the chatbot and perceived usability of the chatbot. The error types of chatbot are divided into 'experience' error and 'agency' error, which set different expectancy level, according to mind perception theory. The structures of error message were either unstructured condition composed of error specification only or structured condition composed of apology, explanation and willingness of improvement. It was found that score of perceived usability was higher in experience error condition than agency error condition. Also, all three scores of dependent variables were higher in structured error message condition than unstructured error message condition. Furthermore, expectation gap of experience didn't predict the dependent variables but expectation gap of agency predicted all three dependent variables. Finally, the tendency of interaction effect between the error type and the structure of the error message on expectation gap of agency was observed. This study confirmed the mitigating effect of structured error messages and the possibility that these effects may vary by the type of error. The result is expected to be applicable to design of error coping strategies that enhance user experience.

A Study on the Safety Design Rule Checking System for Automatic Verification of Design Errors (설계오류 자동 검증을 위한 안전 설계 Rule Checking 체계에 관한 연구)

  • Dukhan Kim;Yuho Yang;Youngwoo Chon
    • Journal of the Society of Disaster Information
    • /
    • v.20 no.1
    • /
    • pp.60-68
    • /
    • 2024
  • Purpose: When designing plants and workplaces such as handling and using chemicals, a system that can automatically determine whether the design has been made in compliance with domestic safety management laws is established to shorten the review time and increase accuracy. Method: Safety design standards for chemical handling and use workplaces were investigated, and types and systems were derived that could automatically judge design errors by dividing the articles into semantic units. Result: An automatic design review method performed when designing a building was proposed, and a system that can review the safety design requirements required when designing a chemical handling business site through the development of a rule checker was proposed. After confirming whether the law is subject to application, the safety design rules are classified into semantic units through preprocessing. The classified results can be classified into four types, and the specifications, space, conditions, situations, and specific devices and facilities to reinforce safety were analyzed as representative types. It proposes a system that prepares a diagram for the safety design rule and allows it to be reviewed through the rule checker program.

Design of CNN Chip with Annealing Capability (어닐링 기능을 갖는 셀룰러 신경망 칩 설계)

  • 유성환;전흥우
    • Journal of the Korean Institute of Telematics and Electronics C
    • /
    • v.36C no.11
    • /
    • pp.46-54
    • /
    • 1999
  • The output values of cellular neural networks would have errors because they can be stabilized at local minimums depending on the initial states of each cell. So, in this paper, we design the $6\times6$cellular neural networks with annealing capability which guarantees that the outputs reaches the global minimum to have correct output values independent of the initial states of each cell. This chip is designed using a $0.8\mu\textrm{m}$ CMOS technology The designed chip contains about 15,000 transistors and the chip size is about $2.89\times2.89\textrm{mm}^2$. The simulation results of edge extraction and hole filling using the designed circuit show that the outputs values would have errors in un-annealed case, but not in annealed case. In the simulation, the annealing time of $3\musec$ is employed.

  • PDF

설계기준해설 - 과거 터널현장 국부적인 붕락 유형 사례 연구

  • Kim, Nak-Yeong;Hwang, Yeong-Cheol
    • 지반과기술
    • /
    • v.10 no.4
    • /
    • pp.20-31
    • /
    • 2013
  • 본 터널 붕락 사례 연구를 종합적으로 분석해 볼때, 시공 공정 중에 발생 가능한 붕괴 및 붕락은 앞서와 같이 과거의 여러 사례들을 토대로 분석함으로서 예측 할 수 있지만, 시공 외적인 요인에 대해서는 사실상 조사, 설계, 시공 중의 오류에 의해 발생되는 것이기 때문에 파악하기 어렵다. 본 터널 붕락사례를 통해 원인을 분석 정리 하면 다음과 같다. (1) 불규칙한 지반구조적 원인 대부분의 터널 붕락을 일으키는 불규칙한 지반구조는 과거 지반구조의 침식 또는 대규모 지반운동 등 지반구조의 급속한 변화에 기인한 것이다. 터널 시공전에 면밀한 사전 지반조사와 선진 보오링 등으로 정확한 지반구조를 파악한다면 이로 인한 터널 붕락은 최소화 시킬수 있다. (2) 기획과 설계단계에서의 오류 충분치 못한 지반조사에 의한 설계 및 부적절한 시공자재 사용등으로 터널 붕락이 발생 될수 있다. 터널 굴착 주변 지반조건과 이러한 지반조건에 적합한 터널 굴착 및 보강공법 등이 터널 설계시 심도있게 검토되어야 할 가장 중요한 요소이다. (3) 시공 및 관리에서의 오류 경험이 부족한 터널기술자의 현장 감독과 현장에서 수집되는 각종 계측자료의 신뢰성 부족과 결과의 재적용 미흡으로 효율적인 계측 및 지반정보를 활용한 정밀 시공이 이루어지지 않는 것도 터널 붕락의 중요한 요인으로 분석되었다. (4) 현장관리 조사서의 표준화 부족 터널굴착공사중 붕락이 발생된 현장의 막장조사결과를 보면 조사자가 임의로 표시를 하여 각 터널별 막장조사결과가 매우 상이할 뿐만 아니라 각 터널별로 기재방법, 양식이 달라서 실제 원인분석에 활용하기가 어려운 것으로 분석되었다.

  • PDF

A Cadence SMV Based Formal Verification Method for Combinational Logics Written in Verilog HDL (Verilog HDL로 기술된 조합 논리회로의 Cadence SMV 기반 정형 검증 방법)

  • Jo, Seong-Deuk;Kim, Young-Kyu;Moon, Byungin;Choi, Yunja
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • 2015.10a
    • /
    • pp.1027-1030
    • /
    • 2015
  • 하드웨어 디자인 설계에서 초기 단계의 설계 오류 발견은 개발 비용 감소 및 설계 시간 단축 측면에서 그 효과가 매우 크다. 이러한 초기 설계 오류 발견을 위한 대표적인 방법으로는 정형 검증(formal verification)이 있으며, Cadence SMV(Symbolic Model Verifier)는 정형 검증을 위해 Verilog HDL(Hardware Description Language)을 SMV로 자동 변환 해주는 장점이 있지만, 사건 기반 구조(event based structures)의 sensitivity list에 대한 지원을 하지 않는 한계가 있다. 이에 본 논문에서는 Cadence SMV에서 디지털회로(digital circuit) 중 하나인 조합 논리회로(combinational logic circuit)를 sensitivity list가 고려된 검증이 가능하도록 하는 방법을 제안한다. 신뢰성 있는 실험을 위해 본 논문에서는 제안하는 방법의 일반적인 규칙을 도출하였고, 도출된 규칙이 적용된 SMV 파일을 생성하는 자동화 프로그램을 구현하여 실험하였다. 실험결과 제안한 방법을 적용한 경우 기존 Cadence SMV가 발견하지 못한 설계상의 오류를 발견할 수 있었다.

A Decision Method of Error Positions Compounding Prigram Slicing Method and Bacdtracking Method (프로그램 슬라이스 기법과 백트랙 기법을 조합한 오류 위치의 결정 방법)

  • Yang, Hae-Sul;Lee, Ha-Yong
    • The Transactions of the Korea Information Processing Society
    • /
    • v.4 no.4
    • /
    • pp.982-992
    • /
    • 1997
  • Almost all the software develpoment cost is especially spwnede in the test phase of kifecycle.Backtracking method and program slicing methed are often used for debugging.But these have need of abundant experience on debuggers or can't apply for large scale programs.In this paper, I used informations of design documents which is generally used, and proposed a new determination method of error positions combining backtracking method and program slcing method.I described several fundamental concepts, error classes, standard design documents and determination method of error positions to porpose a debugging method, and I explained the process of proposed method using an example program with errors.Finally, I compared and analysed the proposed method with usual slicing methods.

  • PDF

Design of False Alerts Reducing Model Using Fuzzy Technique for Intrusion Detection System (퍼지기법을 이용한 침입 탐지 시스템 오류경고메시지 축소 모델 설계)

  • Sung, Kyung
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2007.06a
    • /
    • pp.794-798
    • /
    • 2007
  • As the development of information technology and thus the growth of security incidents, so implement are coming out for defense the intrusion about the system. However the error detection program has got a difficulty to find out the intrusions because that has become so many false alert messages. In this study is how to reduce the messages for the false alerts which come from the internal of the network and using the Fuzzy techniques for reduce the uncertainty of the judge. Therefore it makes the model which can decrease false alert message for better detection.

  • PDF

하드웨어 메모리 스크러버 설계

  • Kim, Dae-Young;Cho, Chang-Burm;Kang, Seok-Ju;Chae, Tae-Byung
    • Aerospace Engineering and Technology
    • /
    • v.2 no.1
    • /
    • pp.73-79
    • /
    • 2003
  • Usual satellite design adopts hardware Error Detection and Correction (EDAC) circuitary for memory elements to endure proper operation in space radiation environment and periodic read-back(scrubbing) scheme to remove errors occurred and to prevent further accumulation of errors, in parallel, But lack of detail radiation test data upset rates of KOMPSAT-2 mass storage was estimated very worse compared to that of KOMPSAT-1, which was evaluated from very precise radiation test. Although upset rates were evaluated enough low to accommodate by KOMPSAT-2 Flight Software, hardware scrubbing scheme is studied to shorten scrubbing time as well. This paper describes hardware scrubbing architecture having minimum 1.88 minutes scrubbing interval over 1 Gbits memory.

  • PDF