• Journal of Korean Society of Coastal and Ocean Engineers
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• v.12 no.4
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• pp.195-202
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• 2000

Recently, wave dissipating structures with porosity are widely used to improve habor tranquility and to reduce the wave overtopping rate. In this study, hydraulic model tests were performed to examine hydraulic efficiency of slit caissons, igloo blocks, and hollow blocks. The model tests showed that slit caissons were the most effective in dissipating wave energy under moderate wave conditions. Slit caissons and igloo blocks showed no significant difference in reducing wave overtopping rate. Hallow blocks are less effective in reducing wave overtopping rate than slit caissons and igloo blocks lU1der higher wave energy conditions.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.489-490
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• 2013

계통 연계형 발전시스템은 스위칭 주파수를 기본으로 하는 배수 고조파들이 발생한다. 이 때 인버터의 출력 전류 고조파는 계통의 전력품질에 영향을 주므로 저역통과 필터를 이용하여 제거해 주어야 한다. 일반적으로 사용하는 L, LC필터는 구성이 간단하고 제어가 용이한 장점이 있지만 동적특성이 좋지 않고 필터의 성능향상을 위해서는 인덕턴스를 증가시켜야 하기 때문에 필터의 부피가 커지는 단점을 가지고 있다. 이에 반해 LCL필터는 LC필터에 비해 더 낮은 용량으로 높은 고조파 감쇄 효과를 구현 할 수 있다는 장점이 있다. 그리고 2레벨 인버터에 비해 3레벨 인버터는 높은 효율과 낮은 THD발생으로 계통 연계 시스템에 많이 적용되고 있다. 본 눈문에서는 계통연계형 3레벨 인버터의 LCL필터 설계를 하여 이를 컴퓨터 시뮬레이션과 실험을 통하여 타당성을 검증한다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.61-66
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• 1983

This paper is concerned with the design of a pseudonoise (PN) sequence used in direct-sequence spread spectrum multiple-access (DS/SSMA) communication systems. Here we propose a new waveform, a generalized version of rectangular waveform, which can reduce the multiple access interference to zero as the pulse width becomes narrower. It gives far better performance than either rectangular or sine waveform.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.8 no.5
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• pp.98-104
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• 2009

In this paper, improved VCO(voltage controlled oscillator) with push-push structure and high impedance-inverter is designed and implemented. Two harmonic oscillators are combined into push-push structure. As a result, the fundamental suppression and the output power have been progressed. For the improved coupling characteristics between hair-pin resonator and two parallel microstrip line using high impedance inverter, the phase noise has been suppressed.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.73-74
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• 2015

H-브릿지 멀티레벨 인버터에서는 계통 전원과의 절연, 각 인버터 Power Cell에 독립된 전원 공급 등의 목적을 위하여 다권선 변압기가 사용된다. 이러한 변압기를 확장 델타 결선 방법의 위상 천이 변압기로 제작할 경우, 멀티레벨 인버터 입력 전류의 고조파 성분을 감쇄시키고 THD를 개선할 수 있다. 본 논문에서는 H-브릿지 멀티레벨 인버터의 확장 델타 변압기를 설계하고, PSIM으로 구성된 시뮬레이션 모델을 사용하여 변압기의 입력단에서 1차단 고조파 성분이 2차단과 비교하여 감쇄되는 것을 확인하도록 한다.

• Journal of IKEEE
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• v.18 no.3
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• pp.313-319
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• 2014

The objectives of power system operations are to preserve system stability and reliability as well as to supply proper electric power. For an activation of these objectives, voltage and reactive power should be considered. There are a number of types about reactive power sources, and an insertion of shunt capacitor banks are one of the method to support bus voltage adjacent. This paper includes the design procedure to determine the hybrid type capacitor bank configurations on power system to improve stability and reliability. This procedure includes the capacitor bank capacity calculation, reactor type selection, and reactor capacity calculation. The total capacity calculation of capacitor bank is based on the reactive power margin which is calculated through system studies such as, contingency analysis and Q-V analysis. In the second step, the reactor type and its capacity can be determined through the harmonic analysis. This paper shows that the harmonics are decreased by the proposed hybrid type capacitor bank, especially 5th and 7th harmonics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.795-802
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• 2011

In this paper, the detailed design procedure of the Y-junction stripline isolator self-contained the filter circuit in the center conductor in order to maximize attenuations below value of 30 dB at 3rd order harmonics is presented. The HFSS is used to simulate 1.8GHz band isolator and the results are compared with the measurement data. These results confirms that the designed stripline isolator is effective in achieving high attenuation above -30 dB at 3rd order harmonics. And it is obtained that the harmonic band of isolator using the ferrite of 0.16T is moved far from operating frequency more 1.2 GHz than one using the ferrite of 0.12T.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.6
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• pp.154-159
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• 2010

In this paper, the magnetically shielded room for low magnetic field shielding is designed and measured by fabricated. The size of magnetically shielded room was 3.0[m](W)$\times$3.0[m](L)$\times$3.0[m](H) to enter the industrial measuring instruments and analyzed DC and AC shielding characteristics of magnetic materials with a high permeability and AC shielding characteristics by eddy current of conductive materials. As a results, shielded room dimensions were obtained. To verify the analysis results, magnetically shielded room is fabricated and the calculated results are compared with the measured results. The Measured results show good agreement with calculated results. According to measurements, 5 times of 0.1[Hz] and 86 times of 60[Hz] is achieved at low frequency. The fabricated shielding room can be used as the magnetically shielding room for low magnetic field shielding.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.11
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• pp.1130-1137
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• 2009

This paper proposes a new clock routing design for suppressing clock harmonic effects in a Printed Circuit Board (PCB) for a terrestrial Digital Multimedia Broadcasting(DMB) system. Typical crystal reference frequencies that are widely used in DMB tuners are 16.384 MHz, 19.2 MHz, 24.576 MHz. When the high-order harmonic components of these reference frequencies fall near the RF channel frequencies, receiver sensitivity of the tuners is seriously degraded. In this work, we propose a new clock routing design in order to address the clock harmonic coupling issue. The proposed design incorporates two inductors for isolating the clock ground from the main ground, and adopts a new strip line-style routing instead of the conventional microstrip line style routing to minimize the overlap area with the main ground. As a result, the RF sensitivity of the T-DMB tuner is improved by 2 dB.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.1
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• pp.83-91
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• 2003

High-speed QPSK demodulator has been in important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes all-digital QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. All-digital QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tacking to fabricate FPGA chip. The testing results of the implemented onto CPLD-EPF10K100GC 503-4 chip show demodulation speed is reached up to 2.6[Mbps]. If it is implemented a CPLD chip with speed grade 1, the demodulation speed can be faster by about 5 times. Actually in case of designing by ASIC, its speed my be faster than CPLD by 5 times. Therefore, it is possible to fabricate the all-digital QPSK demodulator chipset with speed of 50[Mbps].